21.5.5.1.3 PLL Settings
The frequency generated by the PLL is determined by the following control registers:
- PLL REFDIV: The PLL Reference Frequency Divider, 1 ≤ REFDIV ≤ 63
- PLL BWSEL: The PLL Bandwidth Selection, 1 ≤ BWSEL ≤ 4.
- PLLFBDIV: The PLL Feed Back Frequency Divider, 21 ≤ FBDIV ≤ 1023
- POSTDIV: The PLL Output Frequency Divider, 1 ≤ POSTDIV ≤ 63
When the controller is enabled, the relationship between the reference clock frequency and the output clock frequency is given in the equation below:
FCLK_PLL
Where,
- FCLK_PLL is the frequency of the PLL output clock
- FCKR is the frequency of the selected reference clock
- REFDIV is the reference prescaler value
- FBDIV is the loop divider value
- POSTDIV is the output prescaler value
Example: (REFDIV = 2,POSTDIV = 5): assuming fCKR = 4 MHz and fCLK_PLL = 200 MHz, the Feed Back divider FBDIV shall be set to 500.
The frequency after the reference divider (FPDF) is given by the formula:
FPFD = FCKR / REFDIV
The frequency of the Voltage Controlled Oscillator (VCO) giving the PLL oscillation is given by the formula:
FVCO = FCKR * (FBDIV / REFDIV) (must be between 800 MHz and 1600 MHz)
- The PLLREFDIV and PLLFBDIV registers are not write-protected by the PAC. Alternatively, they can be write protected by setting the Control bit ( PLLCTRL.WRTLOCK). When the OSCCTRL is PAC write-protected, the user can still tune the PLL frequency when the PLLCTRL.WRTLOCK is cleared, or the user can also write-protect the PLLREFDIV and PLLFBDIV registers when PLLCTRL.WRTLOCK is set.
- Each PLL has up to four outputs. Each output has an individual PLL output frequency divider POSTDIVn and an individual output control enable OUTENn with n = 0..3. Depending on the selected REFDIV and the reference frequency, the user must set the Band Width Selection bits (BWSEL) in the PLLCTRL register. Refer to the PLLCTRL.BWSEL definition in the “Register Description” section.
