21.5.5.1.4 PLL Lock and Clock Generation

After the PLL oscillator is enabled, the PLL controller waits for the oscillator to issue a Lock status. The PLLLOCK bit in the Status register (STATUS.PLLLOCK) will be set and the PLL controller issue the clock to the system (GCLK). The frequency of the PLL output clock CLK_PLL is stable when the STATUS.PLLLOCK bit is set. The PLL Lock Rising bit (PLLLOCKR) in the INTFLAG register is set when the STATUS.PLLLOCK rises.

Note: During each PLL startup phase, the clock to the internal modules is not delivered as long as the first lock is not detected. When the lock is detected, the clock is released to the GCLK as long as requested.

The PLL Lock Falling bit (PLLLOCKF) in the INTFLAG register is set when the STATUS.PLLLOCK falls.

The PLL outputs whose OUTEN bit are set will start issuing a clock after the rise of the PLL LOCK Status bit (STATUS.PLLLOCK).