29.7.10 Backup Output Control
Note: These register bits are useful for
indicating to users external application logic MCU Backup mode entry/exit.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | BKOUT |
| Offset: | 0x028 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TGLOM1[1:0] | TGLOM0[1:0] | ||||||||
| Access | RW | RW | RW | RW | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SET1 | SET0 | ||||||||
| Access | W | W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CLR1 | CLR0 | ||||||||
| Access | W | W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN1 | EN0 | ||||||||
| Access | RW | RW | |||||||
| Reset | 0 | 0 |
Bits 24:25, 26:27 – TGLOM Toggle Output Mode
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | The output does not toggle. |
| 0x1 | RTCTGL | The output toggles on RTC event. |
| 0x2 | BKUPTGL | The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software. |
Bits 16, 17 – SET Set Output
| Description |
|---|
| Writing a zero to this bit has no effect. |
| Writing a one to this bit will set the corresponding output. |
Bits 8, 9 – CLR Clear Output
| Description |
|---|
| Writing a zero to this bit has no effect. |
| Writing a one to this bit will set the corresponding output. |