33.7.2 ADCON1
| Name: | ADCON1 |
| Offset: | 0xF59 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADPPOL | ADIPEN | ADGPOL | ADDSEN | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – ADPPOL Precharge Polarity bit
| Value | Name | Description |
|---|---|---|
| x | ADPRE = 0 |
Bit has no effect |
| 1 | ADPRE > 0 and ADC input is I/O
pin |
Pin shorted to AVDD |
| 0 | ADPRE > 0 and ADC input is I/O
pin |
Pin shorted to VSS |
| 1 | ADPRE > 0 and ADC input is
internal |
CHOLD shorted to AVDD |
| 0 | ADPRE > 0 and ADC input is
internal |
CHOLD shorted to VSS |
Bit 6 – ADIPEN A/D Inverted Precharge Enable bit
| Value | Name | Description |
|---|---|---|
| x | ADDSEN = 0 |
Bit has no effect |
| 1 | ADDSEN = 1 |
The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle |
| 0 | ADDSEN = 1 |
Both conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL |
Bit 5 – ADGPOL Guard Ring Polarity Selection bit
| Value | Description |
|---|---|
| 1 | ADC guard ring outputs start as digital high during Precharge stage |
| 0 | ADC guard ring outputs start as digital low during Precharge stage |
Bit 0 – ADDSEN Double-Sample Enable bit
| Value | Description |
|---|---|
| 1 | Two conversions are processed as a pair. The selected computation is performed after every second conversion. |
| 0 | Selected computation is performed after every conversion |