The following configuration values are valid for all listed bit names of this register:
0: No alarm generated since the last clear.
1: An alarm has been generated by the corresponding monitor since the last clear.
Name:
SECUMOD_ASR
Offset:
0x000C
Reset:
0x00000000
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
PSWHI
BUHI
Access
R
R
Reset
0
0
Bit
7
6
5
4
3
2
1
0
PSWLO
BULO
TCK
JTAG
REGANA_HI
REGANA_LO
Access
R
R
R
R
R
R
Reset
0
0
0
0
0
0
Bit 9 – PSWHI VDDIN33 (used as
secondary LDO power source through backup power switch) low alarm detected is the cause of
VBATL flag in SECUMOD_SR
Bit 8 – BUHI VBAT high alarm
detected is the cause of VBATH flag in SECUMOD_SR
Bit 7 – PSWLO VDDIN33 (used as
secondary LDO power source through backup power switch) low alarm detected is the cause of
VBATL flag in SECUMOD_SR
Bit 6 – BULO VBAT low alarm
detected is the cause of VBATL flag in SECUMOD_SR
Bit 5 – TCK TCK/TMS activity detected is the cause of JTAG flag
in SECUMOD_SR
Bit 4 – JTAG JTAGSEL or processor debug acknowledge is the cause
of JTAG flag in SECUMOD_SR
Bit 3 – REGANA_HI High voltage alarm
from VDDANA regulator is the cause of REGANA flag in SECUMOD_SR
Bit 2 – REGANA_LO Low voltage alarm
from VDDANA regulator is the cause of REGANA flag in SECUMOD_SR
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
