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8.10.7.5 SECUMOD Status Clear Register The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Clears the corresponding alarm flag bit.
If the corresponding alarm was programmed to generate an SWKUP signal, clearing
the alarm also clears SECUMOD_SYSR.SWKUP.
Name: SECUMOD_SCR Offset: 0x0010 Reset: – Property: Write-only
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 DET3 DET2 DET1 DET0 Access W W W W Reset – – – –
Bit 15 14 13 12 11 10 9 8 VDDCPUH VDDCOREH VDDCPUL VDDCOREL VBATH VBATL Access W W W W W W Reset – – – – – –
Bit 7 6 5 4 3 2 1 0 TPMH TPML REGANA JTAG TST DBLFM DWDT_SW Access R R W W W W W Reset – – – – – – –
Bits 18, 19, 20, 21 – DETx PIOBU Intrusion Detector
Bit 15 – VDDCPUH High VDDCPU Voltage
Monitor
Bit 14 – VDDCOREH High VDDCORE Voltage
Monitor
Bit 13 – VDDCPUL Low VDDCPU Voltage
Monitor
Bit 12 – VDDCOREL Low VDDCORE Voltage
Monitor
Bit 11 – VBATH High VBAT Voltage
Monitor
Bit 10 – VBATL Low VBAT Voltage
Monitor
Bit 7 – TPMH High Temperature
Monitor
Bit 6 – TPML Low Temperature
Monitor
Bit 4 – REGANA VDDANA Regulator
Monitor
Bit 3 – JTAG JTAG Pins Monitor
Bit 2 – TST Test Pin Monitor
Bit 1 – DBLFM Double Frequency
Monitor
Bit 0 – DWDT_SW Programmable Secure Watchdog
Alarm
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