7.6.6 MII/SC-MII Timing

This section specifies the MII/SC-MII transmit and receive timing. Note that timing was designed for system load between 5 pF and 20 pF.

Figure 7-5. MII/SC-MII Transmit Timing
Table 7-13. MII/SC-MII Transmit Timing
DescriptionSymbolMinTypMaxUnits

Additional
Information

TXCLK/SMCLK periodtclkp400nsNote 1
TXCLK/SMCLK high timetclkhtclkp * 0.4tclkp * 0.6nsNote 1
TXCLK/SMCLK low timetclkltclkp * 0.4tclkp * 0.6nsNote 1
TXD[3:0], TXEN setup time to falling edge of TXCLK/SMCLKtsu26.0ns
TXD[3:0], TXEN hold time after falling edge of TXCLK/SMCLKthold0ns
Note:
  1. Design parameter, not tested
Figure 7-6. MII/SC-MII Receive Timing
Table 7-14. MII/SC-MII Receive Timing
DescriptionSymbolMinTypMaxUnits

Additional
Information

RXCLK/SMCLK periodtclkp400nsNote 1
RXCLK/SMCLK high timetclkhtclkp * 0.4tclkp * 0.6nsNote 1
RXCLK/SMCLK low timetclkltclkp * 0.4tclkp * 0.6nsNote 1
RXD[3:0], RXDV, RXER output valid from falling edge of RXCLK/SMCLKtval28.0ns
RXD[3:0], RXDV, RXER output invalid from falling edge of RXCLK/SMCLKtinvld10.0ns
Note:
  1. Design parameter, not tested