36.13.3 ADCCON3 – ADC Control Register 3
- The SAMP bit has the highest priority, and setting this bit keeps the S&H circuit in Sample mode until the bit is cleared. Also, usage of the SAMP bit causes settings of SAMC[9:0] bits (ADCCON2[25:16]) to be ignored.
- The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC.
- The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit and, only after setting the RQCNVRT bit, to start the ADC.
- Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx[4:0] bits and STRGSRC[4:0] bits must be set to ‘
00000
’ to disable all external hardware triggers and prevent them from interfering with the software-controlled sampling command signal SAMP and with the software-controlled trigger RQCNVRT.
Name: | ADCCON3 |
Offset: | 0x1420 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
ADCSEL[1:0] | CONCLKDIV[5:0] | ||||||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DIGEN7 | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
VREFSEL[2:0] | TRGSUSP | UPDIEN | UPDRDY | SAMP | RQCNVRT | ||||
Access | R/W | R/W | R/W | R/W | R/W | R/HS/HC | R/W | R/HS/HC | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
GLSWTRG | GSWTRG | ADINSEL[5:0] | |||||||
Access | R/W | R/W, HC | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:30 – ADCSEL[1:0] Analog-to-Digital Clock Source (TCLK) bits
Value | Description |
---|---|
00 | Peripheral Bus Clock (PB1_CLK) |
01 | FRC Clock |
10 | REFO3 Clock Output |
11 | System Clock (SYS_CLK) |
Bits 29:24 – CONCLKDIV[5:0] Analog-to-Digital Control Clock (TQ) Divider bits
Value | Description |
---|---|
111111 | 64 * TCLK= TQ |
... | — |
000011 | 4 * TCLK= TQ |
000010 | 3 * TCLK= TQ |
000001 | 2 * TCLK= TQ |
000000 | TCLK= TQ |
Bit 23 – DIGEN7 Shared ADC Digital Enable bit
Value | Description |
---|---|
1 | ADC is digital enabled |
0 | ADC is digital disabled |
Bits 15:13 – VREFSEL[2:0] Voltage Reference (VREF) Input Selection bits
VREFSEL[2:0] | ADREF+ | ADREF- |
---|---|---|
000 | AVDD | AVSS |
001-111 | Reserved |
Bit 12 – TRGSUSP Trigger Suspend bit
Value | Description |
---|---|
1 | Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled |
0 | Triggers are not blocked |
Bit 11 – UPDIEN Update Ready Interrupt Enable bit
Value | Description |
---|---|
1 | Interrupt is generated when the UPDRDY bit is set by hardware |
0 | No interrupt is generated |
Bit 10 – UPDRDY ADC Update Ready Status bit
Value | Description |
---|---|
1 | ADC SFRs can be updated |
0 | ADC SFRs cannot be updated |
Bit 9 – SAMP Class 2 and Class 3 Analog Input Sampling Enable bit(1,2,3,4)
Value | Description |
---|---|
1 | The ADC S&H amplifier is sampling |
0 | The ADC S&H amplifier is holding |
Bit 8 – RQCNVRT Individual ADC Input Conversion Request bit
Value | Description |
---|---|
1 | Trigger the conversion of the selected ADC input as specified by the ADINSEL[5:0] bits |
0 | Do not trigger the conversion |
Bit 7 – GLSWTRG Global Level Software Trigger bit
Value | Description |
---|---|
1 | Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either through the associated TRGSRC[4:0] bits in the ADCTRGx registers or through the STRGSRC[4:0] bits in the ADCCON1 register |
0 | Do not trigger an ADC |
Bit 6 – GSWTRG Global Software Trigger bit
This bit is automatically cleared in the next ADC clock cycle.
Value | Description |
---|---|
0 | Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either through the associated TRGSRC[4:0] bits in the ADCTRGx registers or through the STRGSRC[4:0] bits in the ADCCON1 register |
1 | Do not trigger an ADC |
Bits 5:0 – ADINSEL[5:0] Analog Input Select bits
These bits select the analog input to be converted when the RQCNVRT bit is set.
Value | Description |
---|---|
111111 | Reserved |
... | — |
001011 | VDD33/2(AN11) (Internal) |
001010 | VDD 1.2V(VDD_1V2(AN10)) (Internal) |
001001 | ADC Charge-pump 1.2V(CP_1V2(AN9)) (Internal) |
001000 | BandGap Reference (BG_VREF (AN8)) (Internal) |
000111 | AN7 is being monitored |
... | — |
000001 | AN1 is being monitored |
000000 | AN0 is being monitored |