36.13.1 ADCCON1 – ADC Control Register 1

This register controls the basic operation of the ADC module, including behavior in the Sleep and Idle modes and data formatting. This register also specifies the vector shift amounts for the Interrupt Controller.

Name:	ADCCON1
Offset:	0x1400
Reset:	0x00601000
Property:	-


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	FRACT	SELRES[1:0]		STRGSRC[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ON	FRZ	SIDL	AIPMPEN	CVD_EN		FSYUPB	SCANEN
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	7	6	5	4	3	2	1	0
		IRQVS[2:0]			STRGLVL
Access		R/W	R/W	R/W	R/W
Reset		0	0	0	0

Bit 23 – FRACT Fractional Data Output Format bit

Value	Description
0	Integer
1	Fractional

Bits 22:21 – SELRES[1:0] Shared ADC Resolution bits

Note: Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx register. The result occupies 12 bits with the corresponding lower unused bits set to ‘0’. For example, a resolution of 6 bits results in ADCDATAx[5:0] being set to ‘0’ and ADCDATAx[11:6] holding the result.

Value	Description
11	12 bits (default)
10	10 bits
01	8 bits
00	6 bits

Bits 20:16 – STRGSRC[4:0] ScanTrigger Source Select bits

Value	Description
10001 - 11111	Reserved
10000	EVSYS_51
01111	EVSYS_50
01110	EVSYS_49
01101	EVSYS_48
01100	EVSYS_47
01011	EVSYS_46
01010	EVSYS_45
01001	EVSYS_44
01000	EVSYS_43
00111	EVSYS_42
00110	EVSYS_41
00101	EVSYS_40
00100	INT0 External interrupt
00011	Reserved
00010	Global level software trigger (GLSWTRG)
00001	Global software edge trigger (GSWTRG)
00000	No Trigger

Bit 15 – ON ADC Module Enable bit

Note: The ON bit must be set only after the ADC module is configured.

Value	Description
0	ADC module is disabled
1	ADC module is enabled

Bit 14 – FRZ Freeze in Debug Mode

Value	Description
0	Do not freeze in the Debug mode
1	Freeze in the Debug mode

Bit 13 – SIDL Stop in Idle Mode bit

Value	Description
0	Continue module operation in the Idle mode
1	Discontinue module operation when device enters the Idle mode

Bit 12 – AIPMPEN Analog Input charge Pump Enable

Note: The power-up/reset default value is 1’b0.

Bit 11 – CVD_EN CVD Enable (Capacitive Voltage Division Enable) is the bit that enables and starts the CVD operation.

Note:

The software must ensure that prior to enable CVD_EN, the shared ADC core is enabled and ready for conversions; in other words, ADCANCON.ANENx = 1’b1 and ADCANCON.WKRDYx = 1’b1 and ADCCON3.CHN_EN_SHR = 1’b1.
The software must disable all external triggers for all second class channels by setting the corresponding ADCTRGx.TRGSRCx[4:0] = 5’h00 and, also, the third class scan trigger by setting ADCCONx.STRGSRC[4:0] = 5’h00.
The software must enable the ADCCSS1.CSSx channel scan select bits of all the channels to be included in the CVD scan.
The software must set up the Digital Comparator 1 with the necessary comparison values in ADCCMP1 and the required setup in ADCCMPCON1 (enabling the comparator itself as well as its interrupt if desired). The register ADCCMPEN1 is irrelevant for the CVD operation. The Digital Comparator 1 updates its status field ADCCMPCON1.AINID[5:0] with the channel ID just finished for CVD only upon issuing an ADCCMPCON1.DCMPED interrupt signifying a detected touch event. When the CVD accomplishes its purpose (usually after an interrupt request from the Digital Comparator 1 signaling a touch event), the software must clear first the ADCCON3.DIGEN7 bit before clearing CVD_EN. After that, the software may set again ADCCON3.DIGEN7 and start normal A/D conversions on the shared ADC core for all second and third class channels.

Bit 9 – FSYUPB Fast Synchronous UPB Clock bit

Note: ADCCON1.FSYUPB must be ‘0’ when ADCCON1.ADCSEL[1:0] != 0.

Value	Description
0	Fast synchronous UPB clock is disabled
1	Fast synchronous UPB clock is enabled

Bit 8 – SCANEN SCAN Enable bit

Value	Description
0	When this bit is cleared, the scan cycle is re-triggerable, which means that if an edge-sensitive scan trigger arrives in the middle of a current scan cycle, the current conversion completes but the rest of the current scan is aborted, the EOSRDY status bit is asserted and the scan cycle starts again from the beginning with the first channel included in the scan cycle.
1	By setting this bit, the user disallows the scan trigger to re-start the current scan cycle and the current scan cycle completes with its last included channel before getting re-started.

Bits 6:4 – IRQVS[2:0] Interrupt Vector Shift bits

To determine the interrupt vector address, this bit specifies the amount of left-shift done to the ARDYx status bits in the ADCDSTAT1 and ADCDSTAT2 registers prior to adding with the ADCBASE register.

Interrupt Vector Address = Read Value of ADCBASE and Read Value of ADCBASE = Value written to ADCBASE + x << IRQVS[2:0], where ‘x’ is the smallest active input ID from the ADCDSTAT1 or ADCDSTAT2 registers (which has highest priority).

Value	Description
111	Shift x left 7 bit positions
110	Shift x left 6 bit positions
101	Shift x left 5 bit positions
100	Shift x left 4 bit positions
011	Shift x left 3 bit positions
010	Shift x left 2 bit positions
001	Shift x left 1 bit position
000	Shift x left 0 bit positions

Bit 3 – STRGLVL ScanTrigger High Level/Positive Edge Sensitivity bit

Value	Description
0	Scan trigger is positive edge sensitive. When the STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), only a single scan trigger is generated, which completes the scan of all selected analog inputs.
1	Scan trigger is high level sensitive. When the STRIG mode is selected (TRGSRCx[4:0] in the ADCTRGx register), the scan trigger continues for all selected analog inputs, until the STRIG option is removed.