31.3.18.4 Interrupt Flag Register
Note:
- The interrupt flags in this register are set by hardware only.
- Interrupt flags must be cleared and then read back to confirm the clear before exiting the ISR to avoid double interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTFLAG |
| Offset: | 0x0010 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLTCAP | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CRCERR | CRCDONE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERR | SERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 16 – FLTCAP ECC Fault Capture Flag
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will clear the flag.
| Value | Description |
|---|---|
| 0 | No Event. |
| 1 | An ECC Fault Capture, related to FFLTCTRL.FLTMD, has occurred. Write “1” to clear flag. |
Bit 9 – CRCERR CRC Error Flag
Valid when CRCDONE = 1.
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will clear the flag.
| Value | Description |
|---|---|
| 0 | CRCACC Is Equal to the XOR of CRCSUM and CRCFXOR (No CRC Error) |
| 1 | CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR (CRC Error has occurred). Write “1” to clear flag. |
Bit 8 – CRCDONE CRC Calculation Done Flag
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will clear the flag.
| Value | Description |
|---|---|
| 0 | CRC calculation is not done. |
| 1 | CRC calculation is done. Write “1” to clear flag. |
Bit 1 – DERR ECC Double Error Detected Flag
DED events are report in-band with returning read data and will be taken before a interrupt generated from this module.
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will clear the flag.
| Value | Description |
|---|---|
| 0 | No ECC Double Error Detected |
| 1 | ECC Double Error Detected. Write “1” to clear flag. |
Bit 0 – SERR Single Error Corrected Flag
Writing a '0' to this bit has no effect.
Writing a 1 to this bit will clear the flag.
| Value | Description |
|---|---|
| 0 | ECCCTRL.SECCNT Count not reached |
| 1 | ECCCTRL.SECCNT Count reached |