31.3.18.6 Debug Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DBGCTRL |
| Offset: | 0x0018 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DBGECC[1:0] | CRCRUN | ||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 2:1 – DBGECC[1:0] Debug ECC Mode
ECC errors from debugger reads are:
| Value | Description |
|---|---|
| x1 | Not corrected, No Bus Error, INTLFAG is not updated, and FLT logic is not updated. |
| 10 | Corrected, Bus Error, INTFLAG is updated, and FLT logic operates as setup. |
| 00 | Corrected, No Bus ERR, INTFLAG is not updated, and FLT logic is not updated. |
Bit 0 – CRCRUN CRC Debug Run
| Value | Description |
|---|---|
| 0 | CRC Logic Halts in Debug Mode |
| 1 | CRC Logic Runs in Debug Mode |