31.3.18.17 Flash ECC Fault Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FFLTCTRL |
| Offset: | 0x0044 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTMD[2:0] | CTLFLT[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN | FLTRST | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bits 14:12 – FLTMD[2:0] Fault Mode Control
Note: Write Protected when FLTEN = 1.
000 = Fault Injection Disabled
001 = Reserved
010 = Fault Capture Mode Enabled
Capture the address (in FLTADR) and Syndrome in (FLTSYN)
011 =Reserved
100 = Single Fault Injection (at bit selected by FLT1PTR) for Reads
101 = Double Fault Injection for Reads
110 = Single Fault Injection (at bit selected by FLT1PTR) for Writes
111 = Double Fault Injection for Writes
Bits 10:8 – CTLFLT[2:0] ECC/Parity Control Fault Bits
Note: Write Protected when FLTEN = 1.
If FLTMD = 1xx and FLTEN = 1:
| Value | Description |
|---|---|
| 0 | No Fault Injected |
| 1 | Inject a Fault on to the associated ECC/Parity Control bits (CTL[n]) |
Bit 1 – FLTEN ECC Fault Enable Bit
| Value | Description |
|---|---|
| 0 | ECC Fault Injection Disabled |
| 1 | ECC Fault Injection Enabled (module performs operation selected by FLT_MOD) |
Bit 0 – FLTRST Fault Reset
| Value | Description |
|---|---|
| 0 | No Effect |
| 1 | Resets all FLT SFR bits. |