This bit is updated only once after a power-up, (i.e., POR), by hardware when the
LPVREG backup domain regulator is stable and cleared automatically on entry into
either HIBERNATE or BACKUP modes. The internal LPVREG regulator can take several
milliseconds after power-up to stabilize so in case the user’s application
wishes to enter BACKUP mode they should first examine the RSTC.RCAUSE.POR bit.
If set, then poll and wait for PM.INTFLAG.SLEEPRDY = 1 before entering BACKUP
mode. If RSTC.RCAUSE.POR=0 then it’s safe to enter BACKUP mode without polling
PM.INTFLAG.SLEEPRDY.
| Value | Description |
|---|
| 0x0 | Backup LPVREG, (Low Power
Regulator), is not ready. |
| 0x1 | The Backup power domain LPVREG,
(Low Power Regulator), is ready. (1) |
Note:
- Writing a ‘1’ to this bit will clear it.
- Writing a ‘0’ to this bit has no effect.
- This bit is set by hardware only once after a POR.
- The bit is cleared by silicon hardware automatically on entry into
BACKUP or HIBERNATE mode.
