27.12.2 Sleep Configuration

Table 27-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 2:0 – SLEEPMODE[2:0] Sleep Mode

Note:

Due to clock domain synchronization, a small latency occurs between the store instruction and actual writing of the SLEEPCFG.SLEEPMODE[2:0] bits. Software must ensure that the SLEEPCFG register reads the desired SLEEPMODE value before issuing the WFI instruction.
Please refer to the Sleep Modes section for more details on sleep modes definition and behavior.
This register is reset on entry into either HIBERNATE or BACKUP modes.