When entering or exiting HIBERNATE or BACKUP mode, the pin configuration can be
retained based on the state of this bit. This is true on any reset event, other
than a POR, that terminates BACKUP or HIBERNATE mode. This bit is only cleared
on a POR reset or by the user writing a “0 to it.
| Value | Description |
|---|
| 0x0 | When exiting HIBERNATE or BACKUP
mode, the I/O lines configuration is released and driven by the
reset value of the PORT. |
| 0x1 | When exiting HIBERNATE or BACKUP
mode, the configuration of the I/O lines is retained, (i.e.,
stretched), until the IORET bit is written to 0. It allows the
I/O lines to be retained until the application has programmed
the PORT. |
Note:
- This bit is ignored in IDLE, STANDBY and OFF mode. This register/bit is
retained in BACKUP and HIBERNATE mode.
- After setting PM.CTRL.IORET = 1, any subsequent attempt by the user to
change or re-initialize a PORT value, even after a non-POR reset event,
or exit from BACKUP or HIBERNATE by the user, will not present
themselves on the PORT’s until user clears PM.CTRL.IORET bit. The
PM.CTRL.IORET bit is only cleared by silicon hardware on a POR event
which will also reset the PORT values to input, high impedance
state.
- On exit from BACKUP or HIBERNATE mode due to any reset or RTC wake
event, I/O are retained except in the case of a POR event.
- For applicable products with VBAT feature, IO retention (IORET=1) is not
applicable in VBAT backup mode.
