13.6.7 Fault Injection Pointer Register
Note: When protected by PAC or when
MCRAMC_FLTCTRL.FLTEN = 1, any write attempt to this register will fail and return a
bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FLTPTR |
| Offset: | 0x18 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLT2PTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLT1PTR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 23:16 – FLT2PTR[7:0] Double Fault Injection Bit Pointer
Index of the data bit to be flipped during RAM write access at MCRAMC address offset FLTADR for double bit error. Valid values range from 0 to 3871.
Bits 7:0 – FLT1PTR[7:0] Single Fault Injection Bit Pointer
Index of the data bit to be flipped during RAM write access at MCRAMC address offset FLTADR for single and double bit error.
Valid values range from 0 to 3871.