13.6.6 Fault Injection Control Register
Note: When protected by PAC, any write
attempt to this register will fail and return a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FLTCTRL |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTMD[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 13:12 – FLTMD[1:0] Fault Injection Mode
Note: When FLTEN has previously been written to 1, any write attempt to this field
will fail and return a bus error.
| Value | Name | Description |
|---|---|---|
| 00 | DISABLE | Fault Injection Disabled. |
| 01 | SINGLE | Single Fault Injection at bit selected by MCRAMC_FLTPTR.FLT1PTR. |
| 10 | DOUBLE | Double Fault Injection at bits MCRAMC_FLTPTR.FLT1PTR and MCRAMC_FLTPTR.FLT2PTR. |
| 11 | RESERVED | Reserved. |
Bit 1 – FLTEN Fault Injection Enabled
| Value | Description |
|---|---|
| 0 | Disables fault injection. |
| 1 | Enables fault injection at FLTADR address offset as selected by FLTMD and FLTxPTR. |