13.6.3 Interrupt Enable Clear Register
Note: When protected by PAC, any write
attempt to this register will fail and return a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTENCLR |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERREN | SERREN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DERREN Double Bit Error Interrupt Enable Clear
A read returns the Interrupt Enable bit DERREN for the Interrupt Status bit DERR.
Writing a ‘0’ has no effect.
Writing a ‘1’ clears the Interrupt Enable bit DERREN.
Bit 0 – SERREN Single Bit Error Interrupt Enable Clear
A read returns the Interrupt Enable bit SERREN for the Interrupt Status bit SERR.
Writing a ‘0’ has no effect.
Writing a ‘1’ clears the Interrupt Enable bit SERREN.