13.6.1 Control A
Note: When protected by PAC, any write attempt to this register will fail and return a
bus error.
Note: The state of the ENABLE bit at startup depends on the setting of
RAM_INIT_ENB.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000002 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ENABLE | SWRST | ||||||||
| Access | R/W | R/W | |||||||
| Reset | x | 0 |
Bit 1 – ENABLE ECC Decoder Enable
| Value | Description |
|---|---|
| 0 | ECC decoding is disabled. |
| 1 | ECC decoding is enabled. |
Bit 0 – SWRST Software Reset
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Reset the MCRAMC. A software-triggered hardware reset of the MCRAMC user interface is performed. |