13.6.5 Interrupt Status Register
Note: Subsequent to an interrupt flag being cleared, the flag must be read back to
verify the clear before exiting the ISR. Failure to do this can result in duplicate
interrupts.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | INTSTA |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERR | SERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DERR Double Bit Error
Reading a ‘0’ means no double bit error has occurred since the last clearing of this bit.
Reading a ‘1’ means at least one double bit error has occurred since the last clearing of this bit.
Writing a ‘0’ has no effect.
Writing a ‘1’ clears this Interrupt Status bit.
Bit 0 – SERR Single Bit Error
Reading a ‘0’ means no single bit error has occurred since the last clearing of this bit.
Reading a ‘1’ means at least one single bit error has occurred since the last clearing of this bit.
Writing a ‘0’ has no effect.
Writing a ‘1’ clears this Interrupt Status bit.