47.6.15 Event Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EVCTRL |
| Offset: | 0x38 |
| Reset: | 0x00 |
| Property: | Write-Protected, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FPSEEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – FPSEEN Frame pulse event enable bit
This bit is not affected by software reset and should not be changed by software while the SPI_IXS is enabled.
Note:
- This bit is PAC Property protected apb_spiixs_wrprot.
- This bit is Enabled Protected (Writes are ignored when CTRLA.ENABLE = 1) returns a bus error.
| Value | Name | Description |
|---|---|---|
| 0 | Not Enabled | spi_ixs_evt =1’b0 |
| 1 | Enabled | Frame sync/left-right pulse is available to event system. spi_ixs_evt = SSN/FSYNC |