47.6.1 SPI Control Enable Register
Symbol | Description | Symbol | Description | Symbol | Description |
---|---|---|---|---|---|
R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
K | Write to clear | S | Software settable bit | — | — |
Name: | CTRLA |
Offset: | 0x00 |
Reset: | 0x00 |
Property: | PAC Write-Protection |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
RUNSTDBY | ENABLE | SWRST | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 6 – RUNSTDBY Run in Standby Mode Enable Bit
Note: Writing a zero to this bit will disable the standby peripheral, Writing a one
to this bit will enable the peripheral to be put into to standby.
Value | Description |
---|---|
0 | Disable the macro for standby (no standby) |
1 | Enable macro for run standby |
Bit 1 – ENABLE Enable (ON) bit
Note: Writing a zero to this bit will disable the peripheral, Writing a one to this
bit will enable the peripheral.
Value | Description |
---|---|
0 | Turn off and reset macro, disable clocks, disable interrupt event generation, allow SFR modifications. |
1 | Enable macro |
Bit 0 – SWRST SPI Software Reset
Note:
- Writing a one to the SWRST bit resets the state of the module and all the registers, also the hidden registers, in the module to their initial state. The only exception is the DBGSTOP bit, which will keep its value after a SWRST. The module will be disabled after the reset. When writing a one to SWRST, no other bits in the same register will be written, as SWRST will clear all the bits in the same register. After writing a one to SWRST, SWRST will read back one until the module and the registers are reset. Any register write access during the ongoing reset will be discarded and an error will be generated. Read access can be performed without error generated and must return reset value. Writing a one to SWRST will have priority above all other actions, will always happen immediately and never stall the bus.
- Writing a ‘0’ to SWRST has no effect.
- During a SWRST, access to registers/bits without SWRST are disallowed until the CTRLA.SWRST is cleared by hardware.
Value | Description |
---|---|
0 | There is no reset operation ongoing |
1 | The reset operation is ongoing |