47.6.1 SPI Control Enable Register

Table 47-4. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
  RUNSTDBY    ENABLESWRST 
Access R/WR/WR/W 
Reset 000 

Bit 6 – RUNSTDBY Run in Standby Mode Enable Bit

Note: Writing a zero to this bit will disable the standby peripheral, Writing a one to this bit will enable the peripheral to be put into to standby.
ValueDescription
0Disable the macro for standby (no standby)
1Enable macro for run standby

Bit 1 – ENABLE Enable (ON) bit

Note: Writing a zero to this bit will disable the peripheral, Writing a one to this bit will enable the peripheral.
ValueDescription
0Turn off and reset macro, disable clocks, disable interrupt event generation, allow SFR modifications.
1Enable macro

Bit 0 – SWRST SPI Software Reset

Note:
  1. Writing a one to the SWRST bit resets the state of the module and all the registers, also the hidden registers, in the module to their initial state. The only exception is the DBGSTOP bit, which will keep its value after a SWRST. The module will be disabled after the reset. When writing a one to SWRST, no other bits in the same register will be written, as SWRST will clear all the bits in the same register. After writing a one to SWRST, SWRST will read back one until the module and the registers are reset. Any register write access during the ongoing reset will be discarded and an error will be generated. Read access can be performed without error generated and must return reset value. Writing a one to SWRST will have priority above all other actions, will always happen immediately and never stall the bus.
  2. Writing a ‘0’ to SWRST has no effect.
  3. During a SWRST, access to registers/bits without SWRST are disallowed until the CTRLA.SWRST is cleared by hardware.
ValueDescription
0There is no reset operation ongoing
1The reset operation is ongoing