47.6.2 SPI Control Options Select Register

Table 47-5. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Bits 31:30 – MODEEN[1:0] Macro Mode Enabled

Note:

MODE_EN (TPD_EN, TDM_EN, AUDEN) can only be written when Enable =’0’
When AUDEN = 1, MSTEN controls the direction of both SCK and Frame (aka LRC)
FRMEN = 1, When AUDEN = 1 or TDM_EN =1 or TPD_EN=1
When AUDEN = 1, this peripheral functions as if FRMMST = ~MSTEN, regardless of its actual value
When AUDEN = 1, this peripheral functions as if SMP = 0, regardless of its actual value

Value	Description
11	TPD ENABLED (TPD_EN =1)
10	TDM_ENABLED (TDM_EN =1)
01	Enable Audio CODEC Support (AUDEN =1)
00	DEFAULT - AUDEN =0,TDM_EN =0, TPD_EN = 0)

Note:

Can only be written when Enable =’0’, and is not used when using sign extended (SPISGNEXT).
DATAFILL is not applicable for Received data. Only sign extension will.

Value	Description
0	fill undefined bits with“0.”
1	fill undefined bits with“1.”

Note: Can only be written when Enable =’0’.

Value	Description
0	Transmit Under-run last sample send out 0’s
1	Transmit Under-run last sample, send out last sample of the channel (transmits previously received data), if there is no last sample, 0's will be sent out.

Note: Can only be written when Enable=’0’ in audio mode and TPD mode, only a setting of TUSSAMP = 0 should be used.

Value	Description
0	Data is Left Justified (in the upper part for the packed data)
1	Data is Right Justified (in the lower part for the packed data)

Note: Can only be written when Enable=’0’.

Value	Description
0	A TUR is a critical error which stop SPI operation
1	A TUR is NOT a critical error and zeros are transmitted until the SPIxTXB is not empty

Note: Can only be written when Enable=’0’.

The SPI generates a Transmit Service Request when:

Value	Description
11	The SPIxTXB is not full
10	The SPIxTXB is at least half empty
01	The SPIxTXB is empty
00	The SPIxTXB is empty and SPIxSR is empty (i.e. all transmit operations are complete)

Note: Can only be written when Enable=’0’.

Value	Description
0	Idle state for clock is a low level; active state is a high level
1	Idle state for clock is a high level; active state is a low level

Note:

Can only be written when Enable=’0’
When AUDEN = 1, this peripheral functions as if CPHA = 1, regardless of its actual value

Value	Description
0	Transmit happens on transition from active clock state to idle clock state.
1	Transmit happens on transition from idle clock state to active clock state.

Note: Can only be written when Enable=’0’.

Value	Description
0	A ROV is a critical error which stop SPI operation.
1	A ROV is NOT a critical error; during ROV data in the FIFO is not overwritten by receive data.

Note: Can only be written when Enable=’0’.

The SPI generates a Receive Service Request when:

Value	Description
11	The SPIxRXB is full
10	The SPIxRXB is at least half full
01	The SPIxRXB is not empty
00	The SPIxRXB is empty

Note:

Can only be written when Enable=’0’
CLKINDLY[x] is used by the SPI FSM when MSTEN=1 (i.e. the SPI is a clock host). For all other case the value is ignored and the SPI FSM does NOT delay SCK for SDI sampling.
See TscInDly parameter for tap delay resolution