47.6.3 SPI Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | SPICTRL |
| Offset: | 0x08 |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SMP | SPISGNEXT | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CSEN | MSTEN | DISSDO | DISSDI | MODE32 | MODE16 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 10 – SMP SPI Data Input Sample Phase bit
Input data is always sampled at the middle of data output time regardless of the SMP setting in Client Mode.
| Value | Description |
|---|---|
| 0 | Input data sampled at the middle of data output time in Host Mode |
| 1 | Input data sampled at the end of data output time in Host Mode |
Bit 9 – SPISGNEXT Sign Extend Read Data from the RXFIFO
| Value | Description |
|---|---|
| 0 | Data from RX FIFO is not sign extended |
| 1 | Data from RX FIFO is sign extended |
Bit 6 – CSEN Host/Client Mode Select Enable bit
Note:
- When FRMEN = 1, MSSEN is not used
- Use is dependent on MSTEN bit
- Can only be written when Enable =’0’
| Value | Description |
|---|---|
| 0 | Host Mode: Client select SPI support disabled |
| 1 | Host Mode: SPI Client Select support enabled with polarity determined by FRMPOL (SS pin automatically driven during transmission in Host Mode) |
| 0 | Client Mode: SS pin used by the macro in Client mode; (SS pin used as client select input) |
| 1 | Client Mode: SS pin not used by client mode |
Bit 5 – MSTEN Host Mode Enable bit
Note: Can only be written when Enable
=’0’.
| Value | Description |
|---|---|
| 0 | Client Mode |
| 1 | Host Mode |
Bit 4 – DISSDO Disable SDO bit
Note: Can only be written when Enable
=’0’.
| Value | Description |
|---|---|
| 0 | SDO pin is controlled by the macro. |
| 1 | SDO pin is not used by the macro. Pin controlled by PORT function. |
Bit 3 – DISSDI Disable SDI bit
Note: Can only be written when Enable
=’0’.
| Value | Description |
|---|---|
| 0 | SDI pin is controlled by the macro. |
| 1 | SDI pin is not used by the macro. Pin controlled by PORT function. |
Bit 1 – MODE32 Serial Word Length bits for AUDEN=0
| MODE32 - For AUDEN=0 | Communication |
|---|---|
| 1 | 32-bit |
| 0 | 16-bit |
| 0 | 8-bit |
Note:
- Can only be written when Enable =’0’
- Not used when AUDEN=1
- Channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW
Bit 0 – MODE16 Serial Word Length bits for AUDEN=0
| MODE16 - For AUDEN=0 | Communication |
|---|---|
| X | 32-bit |
| 1 | 16-bit |
| 0 | 8-bit |
Note:
- Can only be written when Enable =’0’
- Not used when AUDEN=1
- Channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW