47.6.9 SPI Interrupt Flag Register

Note: In TPD mode is recommended to not enable the devices dedicated as clients interrupts. The SPITUREN, SPIROUEN, and FRMERREN for the Clients should all be disabled and only enable the Host's interrupts as needed.

Note: Interrupt flags must be cleared and then read back to confirm they are cleared before exiting the ISR to avoid double interrupts.

Table 47-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	INTFLAG
Offset:	0x20
Reset:	0x00
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24
		SPIROV			SPITUR
Access		R/W			R/W
Reset		0			0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	FRMERR
Access	R/W
Reset	0


Bit	7	6	5	4	3	2	1	0
				SPITXBE				SPIRXBF
Access				R/W				R/W
Reset				0				0

Bit 30 – SPIROV Receive Overflow Status bit

Note: Cleared only by software, Writing a zero to this bit has no effect, Writing a one to this bit will CLEAR the bit.

Value	Description
0	No overflow
1	A new byte/half-word/word has been completely received when the SPIxRXB was full

Bit 27 – SPITUR Transmit Underrun Status bit

Writing a zero to this bit has no effect.

Writing a one to this bit will SET the Enable bit.

Not cleared with FIFO operation. Only Hardware cleared by the ON bit.

Note:

SPITUR is only valid when FRMEN = 1.
SPITUR is also cleared when ON = 0.
When IGNTUR = 1, SPITUR provides dynamic status of the underrun condition but does not stop Rx/Tx operation and does not need to be cleared by software.