47.6.4 SPI Control Frame Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FRAMECTRL |
| Offset: | 0x0C |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TDMWSZ[2:0] | TDMSSZ[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FRMCNT[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FRMSLV | FRMPOL | FRMCOINC | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FRMSYPW[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 31:29 – TDMWSZ[2:0] TTDM Number of Bits in a Word Size
Note: TDMWSZ can only be written when
ON bit =’0’, and is only valid for TDM_EN = 1.
| Value | Description |
|---|---|
| 111 | Reserved |
| 110 | word size number of bits = 32 |
| 101 | word size number of bits = 28 |
| 100 | word size number of bits = 24 |
| 011 | word size number of bits = 20 |
| 010 | word size number of bits = 16 |
| 001 | word size number of bits = 12 |
| 000 | word size number of bits = 8 |
Bits 26:24 – TDMSSZ[2:0] TTDM Number of Bits in a Slot Size
Note: TDMSSZ can only be written when
ON bit =’0’, and is only valid for TDM_EN = 1.
| Value | Description |
|---|---|
| 111 | Reserved |
| 110 | slot size number of bits = 32 |
| 101 | slot size number of bits = 28 |
| 100 | slot size number of bits = 24 |
| 011 | slot size number of bits = 20 |
| 010 | slot size number of bits = 16 |
| 001 | slot size number of bits = 12 |
| 000 | slot size number of bits = 8 |
Bits 20:16 – FRMCNT[4:0] Frame Sync Pulse Counter
Controls the number of Slots (Serial Words) transmitted per sync pulse.
Note:
- FRMCNT is only valid when FRMEN = 1 (i.e., Framed SPI mode/TDM mode)
- Can only be written when ON bit = ’0’
| Value | Description |
|---|---|
| 10011-11111 | Reserved |
| 10010 | Number of slots per frame sync pulse is 32 |
| 10001 | Number of slots per frame sync pulse is 30 |
| 10000 | Number of slots per frame sync pulse is 28 |
| 01111 | Number of slots per frame sync pulse is 26 |
| 01110 | Number of slots per frame sync pulse is 24 |
| 01101 | Number of slots per frame sync pulse is 22 |
| 01100 | Number of slots per frame sync pulse is 20 |
| 01011 | Number of slots per frame sync pulse is 18 |
| 01010 | Number of slots per frame sync pulse is 16 |
| 01001 | Number of slots per frame sync pulse is 14 |
| 01000 | Number of slots per frame sync pulse is 12 |
| 00111 | Number of slots per frame sync pulse is 10 |
| 00110 | Number of slots per frame sync pulse is 8 |
| 00101 | Number of slots per frame sync pulse is 6 |
| 00100 | Number of slots per frame sync pulse is 5 |
| 00011 | Number of slots per frame sync pulse is 4 |
| 00010 | Number of slots per frame sync pulse is 3 |
| 00001 | Number of slots per frame sync pulse is 2 |
| 00000 | Generate a frame sync pulse on each Serial Word. |
Bit 14 – FRMSLV Frame Sync Pulse Direction Control bit
Note: Can only be written when ON bit
= ’0’.
| Value | Description |
|---|---|
| 0 | Frame sync pulse output (Host) |
| 1 | Frame sync pulse input (Client) |
Bit 13 – FRMPOL Frame Sync/Client Select Polarity bit
Note:
- Can only be written when ON bit = ’0’
- Valid when FRMEN = ‘1’ or SPI Host mode and CSEN = ‘1’
| Value | Description |
|---|---|
| 0 | Frame pulse/Client Select is active low |
| 1 | Frame pulse/Client Select is active high |
Bit 8 – FRMCOINC Frame Sync Pulse Edge Select bit
Note: Can only be written when ON bit
= ’0’.
| Value | Description |
|---|---|
| 0 | Frame synchronization pulse (idle-to-active edge) precedes the first bit clock. |
| 1 | Frame synchronization pulse (idle-to-active edge) coincides with the first bit clock. |
Bits 3:0 – FRMSYPW[3:0] Frame Sync Pulse Width in Serial Words
(As defined by AUDWDMODE[1,0], or MODE[32,16] or TDMSSZ/TDMWSZ for TDM) -- (i.e., Framed SPI Mode, I2S, I8S, TDM,TPD).)
Not all settings are valid for all MODES, and must be set by the user correctly for different MODES like AUDIO, TDM, TPD SPI.
Not all settings are valid for all MODES and must be set by the user correctly for different MODES like AUDIO, TDM, TPD SPI.
Note:
- Can only be written when ON bit =’0’.
- The sync pulse is four Serial Word Length wide used for I8S.
- In TDM mode the serial word length is defined by TDMSSZ/TDMWSZ and not (AUDWDMODE[1:0] or MODE[32,16])
| Value | Description |
|---|---|
| 1011 - 1111 | Reserved |
| 1010 | Frame sync pulse is thirty-two Serial Word (32 slot) Length wide |
| 1001 | Frame sync pulse is sixteen Serial Word (16 slot) Length wide |
| 1000 | Frame sync pulse is eight Serial Word (8 slot) Length wide |
| 0111 | Frame sync pulse is seven Serial Word (7 slot) Length wide |
| 0110 | Frame sync pulse is six Serial Word (6 slot) Length wide |
| 0101 | Frame sync pulse is five Serial Word (5 slot) Length wide |
| 0100 | Frame sync pulse is four Serial Word (4 slot) Length wide |
| 0011 | Frame sync pulse is three Serial Word (3 slot) Length wide |
| 0010 | Frame sync pulse is two Serial Word (2 slot) Length wide |
| 0001 | Frame sync pulse is one Serial Word (1 slot) Length wide |
| 0000 | Frame sync pulse is one clock (SCK) wide |