Bit 0 – SWRSTBSY Software reset busy bit — Synchronizing Busy
bit for SWRST
Note:
Typically, when the SWRST is written, the bit is auto-cleared the APB
clock cycle after. However, the respective SYNCBUSY bit is set and stays
set until the reset in the GCLK domain is not completed. So the user HAS
to poll SYNCBUSY register to know when the operation is complete.
Care must be taken during the APB reset phase, because potentially the
external clock (GCLK) may not present anymore.
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