31.2.23.10 Flash Write Data Register

Table 31-13. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: DATAx
Offset: 0x28 + x*0x04 [x=0..7]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 DATA31DATA30DATA29DATA28DATA27DATA26DATA25DATA24 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 DATA23DATA22DATA21DATA20DATA19DATA18DATA17DATA16 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 DATA15DATA14DATA13DATA12DATA11DATA10DATA9DATA8 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 DATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – DATAx Flash Write Data

The value in this register(s) is written to flash when a Write operation is commanded.

Single Write: (64-bit data)

Writes DATA0 to ADDR[31:3] with address bits [2:0] = 000

Writes DATA1 to ADDR[31:3] with address bits [2:0] = 100

Quad Write: (256-bit data)

Writes DATA0 to ADDR[31:5], with address bits[4:0] = 0_0000

Writes DATA1 to ADDR[31:5], with address bits[4:0] = 0_0100

Writes DATA2 to ADDR[31:5], with address bits[4:0] = 0_1000

Writes DATA3 to ADDR[31:5], with address bits[4:0] = 0_1100

Writes DATA4 to ADDR[31:5], with address bits[4:0] = 1_0000

Writes DATA5 to ADDR[31:5], with address bits[4:0] = 1_0100

Writes DATA6 to ADDR[31:5], with address bits[4:0] = 1_1000

Writes DATA7 to ADDR[31:5], with address bits[4:0] = 1_1100

Note: This field can only be modified when STATUS.BUSY=0.