31.2.23.8 Flash Address Register

Table 31-11. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: ADDR
Offset: 0x0020
Reset: 0x00000000
Property: PAC Write-Protection

Bit 3130292827262524 
 ADDR[31:24] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 ADDR[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 ADDR[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 ADDR[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:0 – ADDR[31:0] Flash Address used by CTRLA.NVMOP

This is a system byte address that the FCW aligns (by dropping lower ordered bits) to the minimum resolution of the NVMOP.

Bulk/Chip/PFM Erase:

Address is ignored

Page Erase:

Address identifies the page to erase

Row Write:

Address identifies the row to write

Single Write: (64-bits)

Address identifies the DWord to write. ADDR[2:0] are ignored

Quad Write: (256-bits)

Address identifies the Quad DWord to write. ADDR[4:0] are ignored

Note:
  1. This field can only be modified when STATUS.BUSY=0.
  2. For 32-bit aligned memory the bottom two bits, ADDR[1:0], are ignored.

    For 64-bit (double word) writes the bottom four bits, ADDR[3:0], are ignored.