35.7.5.3 Control C
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLC |
| Offset: | 0x08 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TXTRHOLD[1:0] | RXTRHOLD[1:0] | FIFOEN | DATA32B | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FMODE | FRMEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IGNTUR | FSPOL | FSLEN | FSES | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ICSPACE[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 31:30 – TXTRHOLD[1:0] Transmit FIFO Threshold
These bits define the threshold for generating the Data Register Empty interrupt and DMA TX trigger.
| TXTRHOLD | Name | Description |
|---|---|---|
| 0 | DEFAULT | Interrupt and DMA triggers can be generated as long as the FIFO is not full. |
| 1 | HALF | Interrupt and DMA triggers are generated when half FIFO space is free. |
| 2 | EMPTY | Interrupt and DMA triggers are generated when the FIFO is empty. |
| 3 | - | Reserved |
Bits 29:28 – RXTRHOLD[1:0] Receive FIFO Threshold
These bits define the threshold for generating the RX Complete interrupt and DMA RX trigger.
| RXTRHOLD | Name | Description |
|---|---|---|
| 0 | DEFAULT | Interrupt and DMA triggers can be generated when a DATA is present in the FIFO. |
| 1 | HALF | Interrupt and DMA triggers can be generated only when the FIFO is half-full. |
| 2 | FULL | Interrupt and DMA triggers can be generated only when the FIFO is full. |
| 3 | - | Reserved |
Bit 27 – FIFOEN FIFO Enable
This bit enables the FIFO operation.
| Value | Description |
|---|---|
| 0 | FIFO operation is disabled |
| 1 | FIFO operation is enabled |
Bit 24 – DATA32B Enable 32-Bit Data
This bit enables 32-bit Extension for read and write transactions to the DATA register.
When disabled, access is according to CTRLB.CHSIZE.
| Value | Description |
|---|---|
| 0 | Transactions from and to DATA register are 8-bit |
| 1 | Transactions from and to DATA register are 32-bit |
Bit 17 – FMODE Frame Mode
This bit defines the Frame Mode.
| FMODE | Name | Description |
|---|---|---|
| 0 | HOST | Frame Host |
| 1 | CLIENT | Frame Client |
Bit 16 – FRMEN Frame Mode Enable
This bit enables the SPI Frame Mode operation.
| FRMEN | Name | Description |
|---|---|---|
| 0 | DISABLE | Frame Mode Disabled |
| 1 | ENABLE | Frame Mode Enabled |
Bit 11 – IGNTUR Ignore Transmit Underrun
This bit controls when the underrun conditions in framed mode must be ignored.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | When a new FSYNC is detected, zero-bytes frames will be sent while underrun condition detection is not cleared. |
| 1 | When a new FSYNC is detected, DATA will be transmitted. |
Bit 10 – FSPOL Frame Synch Polarity
This bit defines the valid Frame Synch polarity.
| FSPOL | Name | Description |
|---|---|---|
| 0 | HIGH | VCC-level valid polarity |
| 1 | LOW | Ground-level valid polarity |
Bit 9 – FSLEN Frame Synch Length
This bit defines the Frame Synch duration.
| FSLEN | Name | Description |
|---|---|---|
| 0 | STROBE | One SCK pulse |
| 1 | LEVEL | One frame duration valid level |
Bit 8 – FSES Frame Sync Edge Select
This bit controls when the frame sync pulse edge must be generated.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | Frame synchronization pulse (idle-to-active edge) precedes the first bit clock. |
| 1 | Frame synchronization pulse (idle-to-active edge) coincides with the first bit clock. |
Bits 5:0 – ICSPACE[5:0] Inter-Character Spacing
When non-zero, CTRLC.ICSPACE selects the minimum number of baud cycles the SCK line will not toggle between characters.
| Value | Description |
|---|---|
| 0x00 | Inter-Character Spacing is disabled |
| 0x01-0x3F | The minimum Inter-Character Spacing |