1.5.4.6 Transceiver Resource Layout

For the PolarFire family of devices, there are between one to six transceiver quads with four transceivers each, for a total of 4 to 24 full-duplex transceiver lanes. There are up to three external reference clock inputs per quad, which can be used with every transmit PLL and transceiver lane CDRs. See Transceiver Clocks for more information.

The transmit PLL output clocks can be used by one or more lanes within a quad, or shared with adjacent quads.

Each receive lane CDR has its own PLL; therefore, all receive rates can run at independent frequencies. For the transmit lanes, one base rate can be created by a transmit PLL and driven to each of the transmit lanes it can connect to. Each lane can select between the base rate of two different transmit PLLs or a divided version (Div2, Div4, Div8, or Div11), which can be selected per transmit lane.

The reference clock to the CDR can be sourced from the FPGA fabric thereby allowing more reference clock sources within a design. The inherent noise from the fabric is tolerated by the CDR.

The following tables list the number of transceiver resources available for each family device.

Table 1-24. PolarFire, PolarFire SoC, and RT PolarFire FPGA Transceiver Resources
DeviceXCVR LanesTxPLLsReference Clock Input Pins
MPF050/MPFS025/MPFS095436 single-ended/3 differential
MPF100/MPFS1608612 single-ended/6 differential
MPF200 1161122 single-ended/11 differential
MPF300/MPFS250 2161122 single-ended/11 differential
MPF500/RTPF500/MPSC460 3241530 single-ended/15 differential
Note:
  1. MPF200-FCG484 and FCVG484 packages only support up to eight XCVR lanes and six TXPLLs.
  2. MPFS250-FCVG484 supports four XCVR lanes (Quad 0 only) and three TXPLLS.
  3. MPFS460 does not have Quad 5.
  4. The FCSG536 package supports four XCVR lanes (Quad 0 only) and three TXPLLS for MPF200T/MPF300T/MPFS095/MPFS160T/MPFS250T.

Figure   2, Figure   3, and Figure   4 show the arrangement of the transceiver quads, the connectivity of lanes, transmit PLLs, and embedded PCIe blocks for the MPF100, MPF200, MPF300, MPF500, and RTPF500 device. This arrangement ensures package compatibility for all of the devices in the PolarFire FPGA family. For example, if a package supports all of the devices of the PolarFire family and a PCIe block is used on the smallest device, then the same PCIe block is available on the same package pins for all other devices in the family.

Figure   1 shows the arrangement of the transceiver quads, the connectivity of lanes, transmit PLLs, and embedded PCIe blocks for the MPFS250T device. This arrangement ensures package compatibility for all of the devices in the PolarFire SoC FPGA family. For example, if a package supports all of the devices of the PolarFire SoC family and a PCIe block is used on the smallest device, then the same PCIe block is available on the same package pins for all other devices in the family.

Figure 1-54. MPF050/MPFS025/MPFS095/MPFS250-FCVG484 and MPF200T/MPF300T/MPFS095/MPFS160T/MPFS250T-FCSG536
Important: The FCSG536 package supports four XCVR lanes (Quad 0 only) and three TXPLLS for MPF200T/MPF300T/MPFS095/MPFS160T/MPFS250T.
Figure 1-55. MPF100/MPF200/MPFS160 Transceiver and Transmit PLL Layout
Figure 1-56. MPF200/MPF300/MPFS250 Transceiver and Transmit PLL Layout
Important:
  • MPF200–FCG484 and FCVG484 only support up to eight XCVR lanes and six TXPLLs. See Figure   2.
  • MPFS250-FCVG484 supports four XCVR lanes (Quad 0 only) and three TXPLLS. See Figure   1.
Figure 1-57. MPF500/RTPF500/MPFS460 Transceiver and Transmit PLL Layout
Important: MPFS460 does not include Quad 5.