16.1.1 Combinatorial Logic

16.1.1.1 AND2

2-Input AND.
Figure 16-2. AND2
Table 16-1. AND2 I/O
Inputs Output
A, B Y
Table 16-2. AND2 Truth Table
A B Y
X 0 0
0 X 0
1 1 1

16.1.1.2 AND3

3-Input AND.
Figure 16-3. AND3
Table 16-3. AND3 I/O
Input Output
A, B, C Y
Table 16-4. AND3 Truth Table
A B C Y
X X 0 0
X 0 X 0
0 X X 0
1 1 1 1

16.1.1.3 AND4

4-Input AND.
Figure 16-4. AND4
Table 16-5. AND4 I/O
Input Output
A, B, C, D Y
Table 16-6. AND4 Truth Table
A B C D Y
X X X 0 0
X X 0 X 0
X 0 X X 0
0 X X X 0
1 1 1 1 1

16.1.1.4 ARI1

The ARI1 macro is responsible for representing all arithmetic operations in the pre-layout phase.
Figure 16-5. ARI1
Table 16-7. ARI1 I/O
InputOutput
A, B, C, D, FCIY, S, FCO

The ARI1 cell has a 20 bit INIT string parameter that is used to configure its functionality. The interpretation of the 16 LSB of the INIT string is shown in the following table. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1.

Table 16-8. Interpretation of 16 LSB of the INIT String for ARI1
ADCBY
0000INIT[0]F0
0001INIT[1]
0010INIT[2]
0011INIT[3]
0100INIT[4]
0101INIT[5]
0110INIT[6]
0111INIT[7]
1000INIT[8]F1
1001INIT[9]
1010INIT[10]
1011INIT[11]
1100INIT[12]
1101INIT[13]
1110INIT[14]
1111INIT[15]
Table 16-9. ARI1 Truth Table for S
YFCIS
000
011
101
110

ARI1 LOGIC

The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the following tables.

Table 16-10. ARI1 INIT[17:16] String Interpretation
INIT[17]INIT[16]G
000
01F0
101
11F1
Table 16-11. ARI1 INIT[19:18] String Interpretation
INIT[19]INIT[18]P
000
01Y
1X1
Table 16-12. FCO Truth Table
PGFCIFCO
0GXG
1XFCIFCI

16.1.1.5 BUFD

Buffer.
Note: The compile optimization does not remove this macro.
Figure 16-6 16-7. BUFD
Table 16-13 16-15. BUFD I/O
Input Output
A Y
Table 16-14 16-16. BUFD Truth Table
A Y
0 0
1 1

16.1.1.6 BUFF

Buffer.
Figure 16-6 16-7. BUFF
Table 16-13 16-15. BUFF I/O
Input Output
A Y
Table 16-14 16-16. BUFF Truth Table
A Y
0 0
1 1

16.1.1.7 CFG1/2/3/4 and Look-Up Tables (LUTs)

CFG1, CFG2, CFG3, and CFG4 are post-layout LUTs that implement any 1-input, 2-input, 3-input, and 4-input combinational logic functions respectively. Each of the CFG1/2/3/4 macros has an INIT string parameter that determines the logic functions of the macro. The output Y is dependent on the INIT string parameter and the values of the inputs.

16.1.1.7.1 CFG2

Post-layout macro implements any 2-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A and B. The INIT string parameter is 4 bits wide.
Figure 16-8. CFG2
Table 16-17. CFG2 I/O
Input Output
A,B Y = f (INIT, A, B)
Table 16-18. CFG2 INIT String Interpretation
BA Y
00 INIT[0]
01 INIT[1]
10 INIT[2]
11 INIT[3]

16.1.1.7.2 CFG3

Post-layout macro used to implement any 3-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, and C. The INIT string parameter is 8 bits wide.
Figure 16-9. CFG3
Table 16-19. CFG3 I/O
Input Output
A, B, C Y = f (INIT, A,B, C)
Table 16-20. CFG3 INIT String Interpretation
CBA Y
000 INIT[0]
001 INIT[1]
010 INIT[2]
011 INIT[3]
100 INIT[4]
101 INIT[5]
110 INIT[6]
111 INIT[7]

16.1.1.7.3 CFG4

Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, C, and D. The INIT string parameter is 16 bits wide.
Figure 16-10. CFG4
Table 16-21. CFG4 I/O
Input Output
A, B, C, D Y = f (INIT, A,B, C, D)
Table 16-22. CFG4 Truth Table
DCBA Y
0000 INIT[0]
0001 INIT[1]
0010 INIT[2]
0011 INIT[3]
0100 INIT[4]
0101 INIT[5]
0110 INIT[6]
0111 INIT[7]
1000 INIT[8]
1001 INIT[9]
1010 INIT[10]
1011 INIT[11]
1100 INIT[12]
1101 INIT[13]
1110 INIT[14]
1111 INIT[15]

16.1.1.8 INV

Inverter.
Figure 16-11. INV
Table 16-23. INV I/O
Input Output
A Y
Table 16-24. INV Truth Table
A Y
0 1
1 0

16.1.1.9 INVD

Inverter.
Note: Compile optimization does not remove this macro.
Figure 16-12. INVD
Table 16-25. INVD I/O
InputOutput
AY
Table 16-26. INVD Truth Table
AY
01
10

16.1.1.10 MX2

2 to 1 Multiplexer.
Figure 16-13. MX2
Table 16-27. MX2 I/O
Input Output
A, B, S Y
Table 16-28. MX2 Truth Table
A B S Y
A X 0 A
X B 1 B

16.1.1.11 MX4

4 to 1 Multiplexer.

This macro uses two logic modules.
Figure 16-14. MX4
Table 16-29. MX4 I/O
Input Output
D0, D1, D2, D3, S0, S1 Y
Table 16-30. MX4 Truth Table
D3 D2 D1 D0 S1 S0 Y
X X X D0 0 0 D0
X X D1 X 0 1 D1
X D2 X X 1 0 D2
D3 X X X 1 1 D3

16.1.1.12 NAND2

2-Input NAND.
Figure 16-15. NAND2
Table 16-31. NAND2 I/O
Input Output
A, B Y
Table 16-32. NAND2 Truth Table
A B Y
X 0 1
0 X 1
1 1 0

16.1.1.13 NAND3

3-Input NAND.
Figure 16-16. NAND3
Table 16-33. NAND3 I/O
Input Output
A, B, C Y
Table 16-34. NAND3 Truth Table
A B C Y
X X 0 1
X 0 X 1
0 X X 1
1 1 1 0

16.1.1.14 NAND4

4-input NAND.
Figure 16-17. NAND4
Table 16-35. NAND4 I/O
Input Output
A, B, C, D Y
Table 16-36. NAND4 Truth Table
A B C D Y
X X X 0 1
X X 0 X 1
X 0 X X 1
0 X X X 1
1 1 1 1 0

16.1.1.15 NOR2

2-input NOR.
Figure 16-18. NOR2
Table 16-37. NOR2 I/O
Input Output
A, B Y
Table 16-38. NOR2 Truth Table
A B Y
0 0 1
X 1 0
1 X 0

16.1.1.16 NOR3

3-input NOR.
Figure 16-19. NOR3
Table 16-39. NOR3 I/O
Input Output
A, B, C Y
Table 16-40. NOR3 Truth Table
A B C Y
0 0 0 1
X X 1 0
X 1 X 0
1 X X 0

16.1.1.17 NOR4

4-input NOR.
Figure 16-20. NOR3
Table 16-41. NOR4 I/O
Input Output
A, B, C, D Y
Table 16-42. NOR4 Truth Table
A B C D Y
0 0 0 0 1
1 X X X 0
X 1 X X 0
X X 1 X 0
X X X 1 0

16.1.1.18 OR2

2-input OR.
Figure 16-21. OR2
Table 16-43. OR2 I/O
Input Output
A, B Y
Table 16-44. OR2 Truth Table
A B Y
0 0 0
X 1 1
1 X 1

16.1.1.19 OR3

3-input OR.
Figure 16-22. OR3
Table 16-45. OR3 I/O
Input Output
A, B, C Y
Table 16-46. OR3 Truth Table
A B C Y
0 0 0 0
X X 1 1
X 1 X 1
1 X X 1

16.1.1.20 OR4

4-input OR.
Figure 16-23. OR4
Table 16-47. OR4 I/O
Input Output
A, B, C, D Y
Table 16-48. OR4 Truth Table
A B C D Y
0 0 0 0 0
1 X X X 1
X 1 X X 1
X X 1 X 1
X X X 1 1

16.1.1.21 XOR2

2-input XOR.
Figure 16-24. XOR2
Table 16-49. XOR2 I/O
Input Output
A, B Y
Table 16-50. XOR2 Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

16.1.1.22 XOR3

3-input XOR.
Figure 16-25. XOR3
Table 16-51. XOR3 I/O
Input Output
A, B, C Y
Table 16-52. XOR3 Truth Table
A B C Y
0 0 0 0
1 0 0 1
0 1 0 1
1 1 0 0
0 0 1 1
1 0 1 0
0 1 1 0
1 1 1 1

16.1.1.23 XOR4

4-input XOR.
Figure 16-26. XOR4
Table 16-53. XOR4 I/O
Input Output
A, B, C, D Y
Table 16-54. XOR4 Truth Table
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

16.1.1.25 XOR8

8-input XOR.

This macro uses two logic modules.
Figure 16-27. XOR8
Table 16-55. XOR8 I/O
Input Output
A, B, C, D, E, F, G, H Y

If you have an odd number of inputs that are High, the output is High (1).

If you have an even number of inputs that are High, the output is Low (0).

For example:

Table 16-56. XOR8 Truth Table
A B C D E F G H Y
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 1 0