16.1.11 Post-Layout Macros

It is a Post-layout macro that stands for Global Buffer. The global clock network is composed of global buffers (GBs) for clock distribution. GBs distribute clocks to the left/right half of the fabric through vertical clock stripes. Each GB drives an independent half-chip global clock (GCLK). Two GBs—one from each half, are instantiated by the Libero SoC PolarFire to distribute a clock to the entire FPGA fabric. There are a total of 24 full-chip global signals and 48 half-chip global signals that may be used in a design. The half-chip globals can be driven by up to 24 fabric routed signals. Clocks driven from regular I/Os, internally generated clocks, and high fan-out signals such as resets can be routed to GBs.

It is a Post-layout macro. Each GB drives row global buffers (RGBs) present on the vertical clock stripes to reach the logic sectors. Each RGB selects a global clock, a regional clock, or a fabric routed clock to drive the logic sectors located on the left or right side of the vertical clock stripe. RGBs are situated on the vertical stripes of the global network architecture inside the FPGA fabric. The global signals from the GBs are routed to the RGBs. Each RGB is independent and can be driven by fabric routing in addition to being driven by GBs. This facilitates the use of RGBs to drive regional clocks spanning a small fabric area, such as the the clock network for SERDES.

The CC_CONFIG macro is a Post-layout macro that is responsible for generating the Carry bit for each ARI1_CC cell in the cluster. CI and CO are the carry-in and carry-out, respectively, to the cell. The intermediate carry-bits are given by CC[11:0]. The functionality of the CC_CONFIG is evaluating CC using CC[n] = !Px!Y3+PxCC[n-1] where, CC[-1] is CI and CC[12] is CO.

Post-layout macro that is a zero input LUT with output tied to either 0 or 1 as per INIT.

The CRN_INT cell is a Post-layout macro that routes clocks from the fabric to corner cells (PLL, DLL).

The ICB_INT cell is a Post-layout macro that routes clocks from fabric to the Interface Clock Block (ICB).

The ICB_CLKINT cell is a Post-layout macro that routes clocks from the Interface Clock Block (ICB) to global buffers.

High-speed I/O bank clock networks are Post-layout macros that are integrated into I/O banks and distribute clocks along the entire I/O bank with low-skew. These are used to clock data in and out of the I/O logic while implementing the high-speed interfaces.

A Post-layout macro that the user can see in NLV. It is remapped to BUFF macros.

A Post-layout macro that the user can see in NLV. It is remapped to BUFF macros.

A Post-layout macro that the user can see in NLV. It is remapped to BUFF macros.

A Post-layout macro that the user can see in NLV. It is remapped to BUFF macros.

A Post-layout macro used to implement a buffer. Output Y= f(A).

A Post-layout macro used to implement a buffer. Output Y= f(B).

A Post-layout macro used to implement a buffer. Output Y= f(C).

A Post-layout macro used to implement a buffer. Output Y= f(D).

Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A. The INIT string parameter is 16 bits wide. Refer to 16.1.1.7.3 CFG4 macro for more details.

Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A. The INIT string parameter is 16 bits wide. Refer to 16.1.11.17 CFG4A macro for more details.

Post-layout macro used to implement any 4-input combinational logic function. Output Y is dependent on the INIT string parameter and the value of A, B, C, and D. The INIT string parameter is 16 bits wide. It has 3 additional outputs IPB, IPC, and IPD and those are inverter outputs for B, C, and D inputs, respectively. Refer to 16.1.1.7.3 CFG4 macro for more details.

Post-layout macro called within RAM64x12. Refer to 16.1.8 RAM64x12 macro for more details. The RAM64x12 macro is designed by using pipeline register and RAM64x12_IP macro.

Post-layout macro for RAM1K20. Refer to 16.1.7 RAM1K20 macro for more details. The RAM1K20 macro is designed by using pipeline register and RAM1K20_IP macro.

It is the Post-layout macro for Multiply and Accumulate (MACC).

Buffer macro available in the post-layout netlist only.

Buffer macro available in the post-layout netlist only. See 16.1.11.23 IOIN_IB for more information.

Buffer macro available in the post-layout netlist with an additional ODT input.

The I/O feed through macro is available in the post-layout netlist only.

The I/O feed through macro is available in the post-layout netlist only.

The I/O differential macro is available in the post-layout netlist (place holder to reserve the N location).

Input I/O macro is available in the post-layout netlist only.

Tri-state output buffer is available in the post-layout netlist only.

The I/O output bypass macro is available in the post-layout netlist only.

The I/O PAD input macro is available in the post-layout netlist only.

The I/O PAD input macro is available in the post-layout netlist only.

The I/O PAD tri-state output macro is available in the post-layout netlist only.

The I/O PAD tri-state output macro is available in the post-layout netlist only.

The I/O PAD bidirectional macro is available in the post-layout netlist only.

The I/O PAD bidirectional macro is available in the post-layout netlist only.

The differential I/O PAD input macro with MIPI low-power escape support available in the post-layout netlist only.

It is a Post-layout macro that is a bidirectional buffer. Refer to 16.1.3.1 BIBUF for more information.

The I/O PAD output macro with the bidirectional input feedback enabled. It is available in the post-layout netlist only.

It is a Post-layout macro similar to IOPAD_FEEDBACK except that input D is inverted inside.

A single post-layout macro for IOINFF, IOUTFF, and IOEFF. The IOD block includes registers for data-in, data-out, and output enable signals. The input registers (IOINFF) provide the registered version of the input signals from the IOA to the FPGA fabric. The output registers (IOUTFF) provide the registered version of the output signals from the FPGA fabric to the IOA. The output enable register (IOENFF) acts as a control signal for the output if the I/O is configured as tri-stated or bidirectional. These registers in IOD blocks are similar to the D-type flip-flops available in fabric logic elements.

It is a Post-layout macro. Each PLL has a programmable delay line that can be configured in the reference clock path or feedback clock path. For PLLs, adding delay in the reference clock path enables clock delay, and adding delay in the feedback clock path enables clock advancement with respect to the reference clock. The PLL must be configured in external feedback mode to add the delay line in the feedback path.

Post-layout macro used to access a transceiver quad memory map using the APB Link protocol.