17.2.1.1 Component Life Cycle

The following steps describe the life cycle of an SoC component and provide instructions on handle data:

1. Generate the component using its configurator in Libero SoC. This generates the following types of data:
   1. HDL files
   2. Memory files
   3. Stimulus and Simulation files
   4. Component metadata such as component file manifest text file, register configuration files (*.reg) for MDDR/FDDR/SerDes and *cfg file for eNVM (SmartFusion 2 and IGLOO 2), uPROM (RTG4), and uPROM and sNVM (PolarFire)
   5. Firmware drivers (*.h) files
   6. Component SDC file
2. For HDL files, instantiate and integrate them in the rest of the HDL design using the external design entry tool/process.
3. Supply memory files and stimulus files to your simulation tool.
4. Supply firmware drivers to your firmware project.
5. Supply Component SDC file to Derive Constraint tool for Constraint Generation. See 17.2.11 Appendix D—Derive Constraints for more details.
6. You must create a second Libero project, where you import the post-Synthesis netlist and your component metadata (data files about the design components, such as register configuration files and initialization files), thus completing the connection between what you generated and what you program.