17.2.1 Overview

While Libero SoC provides a fully-integrated end-to-end design environment to develop SoC and FPGA designs, it also provides the flexibility to run synthesis and simulation with third-party tools outside the Libero SoC environment. However, some design steps must remain within the Libero SoC environment.

The following table lists the major steps in the FPGA design flow and indicates the steps for which Libero SoC must be used.
Table 17-4. FPGA Design Flow
Design Flow StepMust Use LiberoDescription
Design Entry: HDLNoUse third-party HDL editor/checker tool outside Libero® SoC if desired.
Design Entry: ConfiguratorsYesCreate first Libero project for IP catalog core component generation.
Design Entry: System Builder (SmartFusion® 2 and IGLOO® 2 devices only)YesStay in first Libero project.
Automatic PDC/SDC constraint generationNo

Derived constraints need all HDL files and a derive_constraints utility when performed outside of Libero SoC, as described in 17.2.11 Appendix D—Derive Constraints.

SimulationNoUse third-party tool outside Libero SoC, if

desired. Requires download of pre-compiled simulation libraries for target device, target simulator, and target Libero version used for backend implementation.

SynthesisNoUse third-party tool outside Libero SoC if desired.
Design Implementation: Manage Constraints, Compile Netlist, Place-and-Route (see Figure 17-6)YesCreate second Libero project for the backend implementation.
Timing and Power VerificationYesStay in second Libero project.
Configure Design Initialization Data and MemoriesYesUse this tool to manage different types of memories and design initialization in PolarFire®. Stay in second Libero project.
Programming File GenerationYesStay in second Libero project.
Firmware Generation (SmartFusion 2 only)YesStay in second Libero project.
Firmware Debug (SmartFusion 2 only)NoUse third-party tool outside Libero SoC if desired.
Important: You must download precompiled libraries listed under the Compiled Simulation Libraries for SmartFusion® 2, IGLOO® 2, RTG4™ and PolarFire® section on the Libero SoC Documentation page to use a third-party simulator.
In a CPLD/pure Fabric FPGA flow, enter your design using HDL or schematic entry and pass that directly to the synthesis tools. The flow is still supported. However, SmartFusion® 2, IGLOO® 2, RTG4TM, and PolarFire® FPGAs have significant proprietary hard IP blocks requiring the use of configuration cores (SgCores) from the Libero SoC IP catalog. Special handling is required for any blocks that comprise SoC functionality. These are:
  • SmartFusion 2 and IGLOO 2
    • SmartFusion 2 MSS (includes MDDR and eNVM)
    • IGLOO 2 HPMS (includes MDDR and eNVM)
    • System Builder
    • FDDR
    • SerDes
    • Oscillator
    • CCC
    • RAMs (TPSRAM, DPSRAM, URAM)
    • TAMPER, and so on.
  • RTG4
    • uPROM
    • SerDes
    • SerDes INIT
    • FDDR
    • FDDR INIT
    • RCOSC macro
    • CCC
    • RAMs (TPSRAM, DPSRAM, URAM), and so on.
  • PolarFire
    • PF_UPROM
    • PF_SYSTEM_SERVICES
    • PF_CCC
    • PF CLK DIV
    • PF_CRYPTO
    • PF_DRI
    • PF_INIT_MONITOR
    • PF_NGMUX
    • PF_OSC
    • RAMs (TPSRAM, DPSRAM, URAM)
    • PF_SRAM_AHBL_AXI
    • PF_XCVR_ERM
    • PF_XCVR_REF_CLK
    • PF_TX_PLL
    • PF_PCIE
    • PF_IO
    • PF_IOD_CDR
    • PF_IOD_CDR_CCC
    • PF_IOD_GENERIC_RX
    • PF_IOD_GENERIC_TX
    • PF_IOD_GENERIC_TX_CCC
    • PF_RGMII_TO_GMII
    • PF_IOD_OCTAL_DDR
    • PF_DDR3
    • PF_DDR4
    • PF_LPDDR3
    • PF_QDR
    • PF_CORESMARTBERT
    • PF_TAMPER
    • PF_TVS, and so on.

    In addition to the preceding listed SgCores, there are many DirectCore soft IPs available for various device families in the Libero SoC Catalog that use the FPGA fabric resources.

    For design entry, if you use any one of the preceding components, you must use Libero SoC for part of the design entry (17.2.2 Component Configuration), but you can continue the rest of your Design Entry (HDL entry, and so on) outside of Libero. To manage the FPGA design flow outside of Libero, follow the steps provided in the rest of this guide.