17.2.9 Appendix B—Sample SDC and PDC Constraints
(Ask a Question)For certain IP cores such as CCC, OSC, CoreResetP, and CoreConfigP, Libero SoC generates SDC and PDC timing constraints. Passing the SDC and/or PDC constraints to design tools increases the chance of meeting timing closure with less effort and fewer design iterations. The full hierarchical path from the top-level instance is given for all design objects referenced in the constraints.