11.6 Floorplanning Using Chip Planner

In an inclusive region, the Place and Route tool places unassigned logic within its boundary. It can contain macros, both assigned and unassigned to region. Routing resources within an inclusive region are also not restricted. Logic that is placed prior to region creation is not unplaced from the region.

Use the Create Inclusive Region icon

When a region rectangle is created, you can assign logic macros, net macros, and port macros to it from the Design View window.

In an exclusive region, the Place and Route tool does not place unassigned logic within its boundary. It can contain only macros already assigned to the region before the region is created. However, routing resources within an exclusive region are not restricted.

Use the Create Exclusive Region icon to create an exclusive region:

When a region rectangle is created, you can assign logic macros, net macros, and port macros to it from the Design View window.

If an exclusive region rectangle is created over placed macros, the locked macros already inside the exclusive region will not be unplaced. They are automatically assigned to the region. If the macro is placed but not locked, the macros will be unplaced from the locations and will not be assigned to the exclusive region.

In an empty region, neither the user nor the Place and Route tool can place any logic within its boundary. However, routing resources within an empty region can be used by the Place and Route tool.

Use the Create Empty Region icon to create an empty region:

You cannot assign logic macros, net macros, or port macros to an empty region.

If an empty region rectangle is created over placed macros which are not locked, the macros will be unplaced from the locations. The creation of an empty region over locked macros is not allowed.

This option applies to all types of regions: inclusive, exclusive, and empty.

When this check box is checked, the region constraints are applied to routing, in addition to placement. The routing behavior is summarized in the following table for each type of user region.

If your design does not completely use up your target device (for example, 60% utilization or lower), use empty regions to cluster your logic placement into specific subareas of the chip. This helps when you have originally placed-and-routed the design into a smaller device but want to fit it to a larger part while still preserving the performance you have achieved in the smaller device.

Creating empty regions next to the congested area(s) of your design helps reduce congestion. When you place an empty region next to congested logic blocks or regions, the placer cannot place any logic next to your region or logic block. Logic which would normally be placed there is forced to be placed somewhere else. Routing resources next to the congested area are freed up and provide the router more options to route signals into the congested block.

Before deciding to place empty region(s), analyze your design for congestion areas. Use the Ratsnest view in Chip Planner to see dense areas of connectivity into and out of your logic blocks or regions. Create empty regions in these congested areas and see it if improves the routability of your logic.

If you want to preserve the placement of your existing design but plan additional modifications in the future, create empty regions in the areas of the chip where you plan to add additional logic. As you add new logic, remove or resize your empty regions accordingly to fit your new logic. Empty regions placed over I/O pins reserve them for future use as the I/O needs of your design changes. There are some restrictions for using empty regions in this manner.