16.3.4 SRAM

The RAM1K18_RT block contains 24,576 (18,432 with ECC) memory bits and is a true dual-port memory with two independent data ports A and B. The RAM1K18_RT memory can also be configured in two-port mode. All read/write operations to the RAM1K18_RT memory are synchronous. To improve the read-data delay, an optional pipeline register at the output is available. RAM1K18_RT also adds a Read-enable control to both dual-port and two-port modes. The RAM1K18_RT memory has two data ports which can be independently configured in any combination as follows.

• ECC Dual-Port RAM with the following configuration:
  • 1Kx18 on both ports
• Non-ECC Dual-Port RAM with the following configurations:
  • 1Kx18 on both ports
  • 2Kx12 or 2Kx9 on both ports, but port B is read-only
  • 2Kx9 on port A, 1Kx18 on port B
• ECC Two-Port RAM with the following configurations:
  • Any of 512x36 or 1Kx18 on each port
• Non-ECC Two-Port RAM with port A write, port B read:
  • Any of 1Kx18 or 2Kx9 on each port
  • 2Kx12 on both ports
• Non-ECC Two-Port RAM with port A read, port B write:
  • Any of 512x36, 1Kx18, or 2Kx9 on each port

    FUNCTIONALITY

The main features of the RAM1K18_RT memory block are as follows:

• The address, data, block-port select, write enable and read-enable inputs are registered.
• An optional pipeline register with a separate enable and synchronous-reset is available at the read-data port to improve the clock-to-out delay.
• The registers in RAM1K18_RT block have an option to mitigate Single-event transients.
• There is an independent clock for each port. The memory will be triggered at the rising edge of the clock.
• Read from both ports at the same location is allowed.
• Read and write on the same location at the same time results in unknown data to be read. There is no collision prevention or detection. However, correct data are expected to be written into the memory.
• When ECC is enabled, each port of the RAM1K18_RT memory can raise flags to indicate single-bit-correct and double-bit-detect.

The following figure shows a simplified block diagram of the RAM1K18_RT memory block and the following table gives the port descriptions. The simplified block illustrates the two independent data ports and the read-data pipeline registers.

Port Description

A_WIDTH AND B_WIDTH

The following table lists the width/depth mode selections for each port. Two-port mode is in effect when the width of at least one port is 36, and A_WIDTH indicates the read width while B_WIDTH indicates the write width.

A_WEN AND B_WEN

The following table lists the write/read control signals for each port. Two-port mode is in effect when the width of at least one port is 36, and read operation is always enabled.

A_ADDR AND B_ADDR

The following table lists the address buses for the two ports. 11 bits are needed to address the 2K independent locations in x9 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0. A_ADDR is synchronized by A_CLK while B_ADDR is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_ADDR provides the read-address while B_ADDR provides the write-address.

A_DIN AND B_DIN

The following table lists the data input buses for the two ports. The required bits are LSB justified and unused MSB bits must be tied to 0. Two-port mode is in effect when the width of at least one port is 36, and A_DIN provides the MSB of the write-data while B_DIN provides the LSB of the write-data.

A_DOUT AND B_DOUT

The following table lists the data output buses for the two ports. The required bits are LSB justified. Two-port mode is in effect when the width of at least one port is 36, and A_DOUT provides the MSB of the read-data while B_DOUT provides the LSB of the read-data.

A_BLK AND B_BLK

The following table lists the block-port select control signals for the two ports. A_BLK is synchronized by A_CLK while B_BLK is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_BLK controls the read operation while B_BLK controls the write operation.

A_WMODE AND B_WMODE

Specifies the write mode for each port:

• Logic 00 = Read-data port holds the previous value.
• Logic X1 = This setting is invalid.
• Logic 10 = This setting is invalid.

  A_CLK AND B_CLK

All signals in ports A and B are synchronous to the corresponding port clock. All addresses, data, block-port select, write enable, and read-enable inputs must be setup before the rising edge of the clock. The read or write operation begins with the rising edge. Two-port mode is in effect when the width of at least one port is 36, and A_CLK provides the read clock while B_CLK provides the write clock.

A_REN AND B_REN

Enables read operation from the memory on the corresponding port.

Read-data Pipeline Register Control signals

• A_DOUT_BYPASS and B_DOUT_BYPASS
• A_DOUT_EN and B_DOUT_EN
• A_DOUT_SRST_N and B_DOUT_SRST_N

Two-port mode is in effect when the width of at least one port is 36, and the A_DOUT register signals control the MSB of the read-data while the B_DOUT register signals control the LSB of the read-data.

The following table describes the functionality of the control signals on the A_DOUT and B_DOUT pipeline registers.

ARST_N

Connects the Read-data pipeline registers to the global Asynchronous-reset signal.

ECC AND ECC_DOUT_BYPASS

Controls ECC operation.

• ECC = 0: Disable ECC.
• ECC = 1, ECC_DOUT_BYPASS = 0: Enable ECC Pipelined.
• ECC Pipelined mode inserts an additional clock cycle to Read-data.
  • ECC = 1, ECC_DOUT_BYPASS = 1: Enable ECC Non-pipelined.

    A_SB_CORRECT AND B_SB_CORRECT

Output flag indicates single-bit correction was performed on the corresponding port.

A_DB_DETECT AND B_DB_DETECT

Output flag indicates double-bit detection was performed on the corresponding port.

DELEN

Enable Single-event Transient mitigation.

SECURITY

Controls signal, when 1 locks the entire RAM1K18_RT memory from being accessed by the SII.

BUSY

This output indicates that the RAM1K18_RT memory is being accessed by the SII.

The RAM64x18_RT block contains 1,536 (1,152 with ECC) memory bits and is a three-port memory providing one write port and two read ports. Write operations to the RAM64x18_RT memory are synchronous. Read operations can be asynchronous or synchronous for setting up the address and reading out the data. Enabling synchronous operation at the read-address port improves setup timing for the read-address and its enable signals. Enabling synchronous operation at the read-data port improves clock-to-out delay. Each data port on the RAM64x18_RT memory can be independently configured in any combination as follows.

• ECC Three-Port RAM with the following configuration:
  • 64x18 on all three ports
• Non-ECC Three-Port RAM with the following configurations:
  • Any of 64x18 or 128x9 on each port
  • 128x12 on all three ports

    FUNCTIONALITY

The main features of the RAM64x18_RT memory block are as follows.

• There are two independent read-data ports A and B, and one write-data port C.
• The write operation is always synchronous. The write-address, write-data, C block-port select and write enable inputs are registered.
• For both read-data ports, setting up the address can be synchronous or asynchronous.
• The two read-data ports have address registers with a separate enable and synchronous-reset for synchronous mode operation, which can also be bypassed for asynchronous mode operation.
• The two read-data ports have output registers with a separate enable and synchronous-reset for pipeline mode operation, which can also be bypassed for asynchronous mode operation.
• Therefore, there are four read operation modes for ports A and B:
  • Synchronous read-address without read-data pipeline registers (sync-async)
  • Synchronous read-address with read-data pipeline registers (sync-sync)
  • Asynchronous read-address without read-data pipeline registers (async-async)
  • Asynchronous read-address with read-data pipeline registers (async-sync)
• In ECC mode, all ports have word widths equal to 18 bits.
• In non-ECC mode, each port can be independently configured to any of the following depth/width: 64x18 or 128x9. In addition, all the ports can be configured to 128x12.
• The registers in RAM64x18_RT block have an option to mitigate Single-event transients.
• There is an independent clock for each port. The memory will be triggered at the rising edge of the clock.
• Read from both ports A and B at the same location is allowed.
• Read and write on the same location at the same time results in unknown data to be read.
• There is no collision prevention or detection. However, correct data are expected to be written into the memory.
• When ECC is enabled, each port of the RAM64x18_RT memory can raise flags to indicate single-bit-correct and double-bit-detect.

The following figure shows a simplified block diagram of the RAM64x18_RT memory block and the following table gives the port descriptions. The simplified block illustrates the three independent read/write ports and the pipeline registers on the read port.

PORT DESCRIPTION

A_WIDTH, B_WIDTH AND C_WIDTH

The following table lists the width/depth mode selections for each port.

C_WEN

This is the write enable signal for port C.

A_ADDR, B_ADDR AND C_ADDR

The following table lists the address buses for each port. 7 bits are required to address 128 independent locations in x9 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0.

C_DIN

The following table lists the write-data input for port C. The required bits are LSB justified and unused MSB bits must be tied to 0.

A_DOUT AND B_DOUT

The following table lists the read-data output buses for ports A and B. The required bits are LSB justified.

A_BLK, B_BLK AND C_BLK

The following table lists the block-port select control signals for the ports.

C_CLK

All signals on port C are synchronous to this clock signal. All write-address, write-data, C block-port select and write-enable inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge.

Read-address and Read-data Pipeline Register Control signals

• A_DOUT_BYPASS, A_ADDR_BYPASS, B_DOUT_BYPASS, and B_ADDR_BYPASS
• A_DOUT_EN, A_ADDR_EN, B_DOUT_EN, and B_ADDR_EN
• A_DOUT_SRST_N, A_ADDR_SRST_N, B_DOUT_SRST_N, and B_ADDR_SRST_N

The following table describes the functionality of the control signals on the A_ADDR, B_ADDR, A_DOUT, and B_DOUT registers.

ARST_N

Connects the read-address and read-data pipeline registers to the global Asynchronous-reset signal.

ECC and ECC_DOUT_BYPASS

Controls ECC operation.

• ECC = 0: Disable ECC.
• ECC = 1, ECC_DOUT_BYPASS = 0: Enable ECC Pipelined.
  • ECC Pipelined mode inserts an additional clock cycle to Read-data.
• ECC = 1, ECC_DOUT_BYPASS = 1: Enable ECC Non-pipelined.

  A_SB_CORRECT AND B_SB_CORRECT

Output flag indicates single-bit correction was performed on the corresponding port.

A_DB_DETECT and B_DB_DETECT

Output flag indicates double-bit detection was performed on the corresponding port.

DELEN

Enable Single-event Transient mitigation.

SECURITY

Control signal, when 1 locks the entire RAM64x18_RT memory from being accessed by the SII.

BUSY

This output indicates that the RAM64x18_RT memory is being accessed by the SII.