16.3.2 hm4

16.3.2.1 INV

Inverter.
Figure 16-200. INV
Table 16-414. INV I/O
Input Output
A Y
Table 16-415. INV Truth Table
A Y
0 1
1 0

16.3.2.2 INVD

Inverter.
Note: Compile optimization does not remove this macro.
Figure 16-201. INVD
Table 16-416. INVD I/O
InputOutput
AY
Table 16-417. INVD Truth Table
AY
01
10

16.3.2.3 MX2

2 to 1 Multiplexer.
Figure 16-202. MX2
Table 16-418. MX2 I/O
Input Output
A, B, S Y
Table 16-419. MX2 Truth Table
A B S Y
A X 0 A
X B 1 B

16.3.2.4 MX4

4 to 1 Multiplexer.

This macro uses two logic modules.
Figure 16-203. MX4
Table 16-420. MX4 I/O
Input Output
D0, D1, D2, D3, S0, S1 Y
Table 16-421. MX4 Truth Table
D3 D2 D1 D0 S1 S0 Y
X X X D0 0 0 D0
X X D1 X 0 1 D1
X D2 X X 1 0 D2
D3 X X X 1 1 D3

16.3.2.5 NAND2

2-Input NAND.
Figure 16-204. NAND2
Table 16-422. NAND2 I/O
Input Output
A, B Y
Table 16-423. NAND2 Truth Table
A B Y
X 0 1
0 X 1
1 1 0

16.3.2.6 NAND3

3-Input NAND.
Figure 16-205. NAND3
Table 16-424. NAND3 I/O
Input Output
A, B, C Y
Table 16-425. NAND3 Truth Table
A B C Y
X X 0 1
X 0 X 1
0 X X 1
1 1 1 0

16.3.2.7 NAND4

4-input NAND.
Figure 16-206. NAND4
Table 16-426. NAND4 I/O
Input Output
A, B, C, D Y
Table 16-427. NAND4 Truth Table
A B C D Y
X X X 0 1
X X 0 X 1
X 0 X X 1
0 X X X 1
1 1 1 1 0

16.3.2.8 NOR2

2-input NOR.
Figure 16-207. NOR2
Table 16-428. NOR2 I/O
Input Output
A, B Y
Table 16-429. NOR2 Truth Table
A B Y
0 0 1
X 1 0
1 X 0

16.3.2.9 NOR3

3-input NOR.
Figure 16-208. NOR3
Table 16-430. NOR3 I/O
Input Output
A, B, C Y
Table 16-431. NOR3 Truth Table
A B C Y
0 0 0 1
X X 1 0
X 1 X 0
1 X X 0

16.3.2.10 NOR4

4-input NOR.
Figure 16-209. NOR3
Table 16-432. NOR4 I/O
Input Output
A, B, C, D Y
Table 16-433. NOR4 Truth Table
A B C D Y
0 0 0 0 1
1 X X X 0
X 1 X X 0
X X 1 X 0
X X X 1 0

16.3.2.11 OR2

2-input OR.
Figure 16-210. OR2
Table 16-434. OR2 I/O
Input Output
A, B Y
Table 16-435. OR2 Truth Table
A B Y
0 0 0
X 1 1
1 X 1

16.3.2.12 OR3

3-input OR.
Figure 16-211. OR3
Table 16-436. OR3 I/O
Input Output
A, B, C Y
Table 16-437. OR3 Truth Table
A B C Y
0 0 0 0
X X 1 1
X 1 X 1
1 X X 1

16.3.2.13 OR4

4-input OR.
Figure 16-212. OR4
Table 16-438. OR4 I/O
Input Output
A, B, C, D Y
Table 16-439. OR4 Truth Table
A B C D Y
0 0 0 0 0
1 X X X 1
X 1 X X 1
X X 1 X 1
X X X 1 1

16.3.2.14 XOR2

2-input XOR.
Figure 16-213. XOR2
Table 16-440. XOR2 I/O
Input Output
A, B Y
Table 16-441. XOR2 Truth Table
A B Y
0 0 0
0 1 1
1 0 1
1 1 0

16.3.2.15 XOR3

3-input XOR.
Figure 16-214. XOR3
Table 16-442. XOR3 I/O
Input Output
A, B, C Y
Table 16-443. XOR3 Truth Table
A B C Y
0 0 0 0
1 0 0 1
0 1 0 1
1 1 0 0
0 0 1 1
1 0 1 0
0 1 1 0
1 1 1 1

16.3.2.16 XOR4

4-input XOR.
Figure 16-215. XOR4
Table 16-444. XOR4 I/O
Input Output
A, B, C, D Y
Table 16-445. XOR4 Truth Table
A B C D Y
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

16.3.2.17 XOR8

8-input XOR.

This macro uses two logic modules.
Figure 16-216. XOR8
Table 16-446. XOR8 I/O
Input Output
A, B, C, D, E, F, G, H Y

If you have an odd number of inputs that are High, the output is High (1).

If you have an even number of inputs that are High, the output is Low (0).

For example:

Table 16-447. XOR8 Truth Table
A B C D E F G H Y
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 1 0

16.3.2.18 UJTAG

The UJTAG macro is a special purpose macro. It allows access to the user JTAG circuitry on board the chip. You must instantiate a UJTAG macro in your design if you plan to make use of the user JTAG feature. The TMS, TDI, TCK, TRSTB, and TDO pins of the macro must be connected to top level ports of the design.

Figure 16-217. UJTAG
Table 16-448. Ports and Descriptions
PortDirectionPolarityDescription
UIREG[7:0]Output—This 8-bit bus carries the contents of the JTAG instruction register of each device. Instruction values 16 to 127 are not reserved and can be employed as user-defined instructions.
URSTBOutputLowURSTB is an Active-Low signal and is asserted when the TAP controller is in Test-Logic-Reset mode. URSTB is asserted at power-up, and a Power-on Reset signal resets the TAP controller state.
UTDIOutput—This port is directly connected to the TAP's TDI signal.
UTDOInput—This port is the user TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR addess is in user range.
UDRSHOutputHighActive-High signal enabled in the Shift_DR TAP state.
UDRCAPOutputHighActive-High signal enabled in the Capture_DR_TAP state.
UDRCKOutput—This port is directly connected to the TAP's TCK signal.
UDRUPDOutputHighActive-High signal enabled in the Update_DR_TAP state.
TCKInput—Test Clock

Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/pull-down resistor. Connect TCK to GND or 3.3V through a resistor (500–1 KΩ) placed closed to the FPGA pin to prevent totem-pole current on the input buffer and TMS from entering into an undesired state.

If JTAG is not used, connect it to GND.

TDIInput—Test Data in. Serial input for JTAG boundary scan. There is an internal weak pull-up resistor on the TDI pin.
TDOOutput—Test Data Out. Serial output for JTAG boundary scan. The TDO pin does not have an internal pull-up/pull-down resistor.
TMSInput—Test mode select. The TMS pin controls the use of the IEEE® 1532 boundary scan pins (TCK, TDI, TDO, and TRST). There is an internal weak pull-up resistor on the TMS pin.
TRSTBInputLowTest reset. The TRSTB pin is an active-low input. It synchronously initializes (or resets) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin.

To hold the JTAG in reset mode and prevent it from entering into undesired states in critical applications, connect TRSTB to GND through a 1 KΩ resistor (placed close to the FPGA pin).