17.2.11.1.1 Working with the derive_constraints Utility

Derive constraints traverse through the design and allocate new constraints for each instance of component based on previously provided component SDC/NDC/PDC files. For the CCC reference clocks, it propagates back through the design to find the source of the reference clock. If the source is an I/O, the reference clock constraint will be set on the I/O. If it is a CCC output or another clock source (for example, SerDes, oscillator), it uses the clock from the other component and reports a warning if the intervals do not match. Derive constraints will also allocate constraints for some macros like on-chip oscillators if you have them in your RTL.

To execute the derive_constraints utility, you must supply a .tcl file command-line argument with the following information in the specified order.

  1. Specify device information using the information in section 17.2.11.1.2 set_device.
  2. Specify path to the RTL files using the information in section 17.2.11.1.3 read_verilog or 17.2.11.1.4 read_vhdl.
  3. Set top level module using the information in section 17.2.11.1.5 set_top_level.
  4. Specify path to the component SDC/NDC files using the information in section 17.2.11.1.6 read_sdc or 17.2.11.1.7 read_ndc.
  5. Execute the files using the information in section 17.2.11.1.8 derive_constraints.
  6. Specify path to the SDC/PDC/NDC derived constraints file using the information in section 17.2.11.1.9 write_sdc or 17.2.11.1.10 write_pdc or 17.2.11.1.11 write_ndc.

Execution and Contents of the derive.tcl File

The following is an example command-line argument to execute the derive_constraints utility.

$ <libero_installation_path>/bin{64}/derive_constraints derive.tcl

The contents of the derive.tcl file:

# Device information set_device -family PolarFire -die MPF100T -speed -1 # RTL files read_verilog -mode system_verilog project/component/work/txpll0/txpll0_txpll0_0_PF_TX_PLL.v read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v} read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/xcvr0_I_XCVR_PF_XCVR.v} read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v} read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd} #Component SDC files set_top_level {xcvr1} read_sdc -component {project/component/work/txpll0/txpll0_0/txpll0_txpll0_0_PF_TX_PLL.sdc} read_sdc -component {project/component/work/xcvr0/I_XCVR/xcvr0_I_XCVR_PF_XCVR.sdc} #Use derive_constraint command derive_constraints #SDC/PDC/NDC result files write_sdc {project/constraint/xcvr1_derived_constraints.sdc} write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}