11.13.26 PIR3

Peripheral Interrupt Request Register 3

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared.
SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR3
Address:	0x4B1


Bit	7	6	5	4	3	2	1	0
	TMR0IF	CCP1IF	TMR1GIF	TMR1IF	TMR2IF	SPI1IF	SPI1TXIF	SPI1RXIF
Access	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – TMR0IF TMR0 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – CCP1IF CCP1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – TMR1GIF TMR1 Gate Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – TMR1IF TMR1 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – TMR2IF TMR2 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 2 – SPI1IF SPI1 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – SPI1TXIF SPI1 Transmit Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – SPI1RXIF SPI1 Receive Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. SPI1IF is a read-only bit. To clear the interrupt condition, all bits in the SPI1INTF register must be cleared. SPI1TXIF and SPI1RXIF are read-only bits and cannot be set/cleared by software.