11.13.31 PIR8

Peripheral Interrupt Request Register 8

Note:

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
U2IF is a read-only bit. To clear the interrupt condition, all bits in the U2UIR register must be cleared.
U2EIF is a read-only bit. To clear the interrupt condition, all bits in the U2ERR register must be cleared.
U2TXIF and U2RXIF are read-only bits and cannot be set/cleared by software.

Name:	PIR8
Address:	0x4B6


Bit	7	6	5	4	3	2	1	0
	SCANIF	CCP2IF	TMR5GIF	TMR5IF	U2IF	U2EIF	U2TXIF	U2RXIF
Access	R/W/HS	R/W/HS	R/W/HS	R/W/HS	R	R	R	R
Reset	0	0	0	0	0	0	0	0

Bit 7 – SCANIF Memory Scanner Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 6 – CCP2IF CCP2 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 5 – TMR5GIF TMR5 Gate Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 4 – TMR5IF TMR5 Interrupt Flag

Value	Description
1	Interrupt has occurred (must be cleared by software)
0	Interrupt event has not occurred

Bit 3 – U2IF UART2 Interrupt Flag⁽²⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 2 – U2EIF UART2 Framing Error Interrupt Flag⁽³⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 1 – U2TXIF UART2 Transmit Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Bit 0 – U2RXIF UART2 Receive Interrupt Flag⁽⁴⁾

Value	Description
1	Interrupt has occurred
0	Interrupt event has not occurred

Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U2IF is a read-only bit. To clear the interrupt condition, all bits in the U2UIR register must be cleared. U2EIF is a read-only bit. To clear the interrupt condition, all bits in the U2ERR register must be cleared. U2TXIF and U2RXIF are read-only bits and cannot be set/cleared by software.