11.13.37 PIR14

Peripheral Interrupt Request Register 14
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name: PIR14
Address: 0x4BC

Bit 76543210 
 DMA7AIFDMA7ORIFDMA7DCNTIFDMA7SCNTIFNCO3IFCM2IFCLC7IF  
Access R/WR/WR/WR/WR/W/HSR/W/HSR/W/HS 
Reset 0000000 

Bit 7 – DMA7AIF DMA7 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA7ORIF DMA7 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – DMA7DCNTIF DMA7 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – DMA7SCNTIF DMA7 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – NCO3IF NCO3 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – CM2IF CMP2 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 1 – CLC7IF CLC7 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.