11.13.34 PIR11

Peripheral Interrupt Request Register 11
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name: PIR11
Address: 0x4B9

Bit 76543210 
 DMA4AIFDMA4ORIFDMA4DCNTIFDMA4SCNTIFTMR4IFCWG3IFCLC6IFCCP3IF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 7 – DMA4AIF DMA4 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA4ORIF DMA4 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – DMA4DCNTIF DMA4 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – DMA4SCNTIF DMA4 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – TMR4IF TMR4 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 2 – CWG3IF CWG3 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 1 – CLC6IF CLC6 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 0 – CCP3IF CCP3 Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.