11.13.25 PIR2

Peripheral Interrupt Request Register 2
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Name: PIR2
Address: 0x4B0

Bit 76543210 
 DMA1AIFDMA1ORIFDMA1DCNTIFDMA1SCNTIFADCH4IFADCH3IFADCH2IFADCH1IF 
Access R/W/HSR/W/HSR/W/HSR/W/HSR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – DMA1AIF DMA1 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA1ORIF DMA1 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 5 – DMA1DCNTIF DMA1 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 4 – DMA1SCNTIF DMA1 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 3 – ADCH4IF ADC Context 4 Threshold Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – ADCH3IF ADC Context 3 Threshold Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – ADCH2IF ADC Context 2 Threshold Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – ADCH1IF ADC Context 1 Threshold Interrupt Flag

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.