11.13.35 PIR12

Peripheral Interrupt Request Register 12
Note:
  1. Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
  2. U4IF is a read-only bit. To clear the interrupt condition, all bits in the U4UIR register must be cleared.
  3. U4EIF is a read-only bit. To clear the interrupt condition, all bits in the U4ERR register must be cleared.
  4. U4TXIF and U4RXIF are read-only bits and cannot be set/cleared by software.
Name: PIR12
Address: 0x4BA

Bit 76543210 
 DMA5AIFDMA5ORIFDMA5DCNTIFDMA5SCNTIFU4IFU4EIFU4TXIFU4RXIF 
Access R/W/HSR/W/HSR/W/HSR/W/HSRRRR 
Reset 00000000 

Bit 7 – DMA5AIF DMA5 Abort Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 6 – DMA5ORIF DMA5 Overrun Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 5 – DMA5DCNTIF DMA5 Destination Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 4 – DMA5SCNTIF DMA5 Source Count Interrupt Flag

ValueDescription
1 Interrupt has occurred (must be cleared by software)
0 Interrupt event has not occurred

Bit 3 – U4IF  UART 4 Interrupt Flag(2)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 2 – U4EIF  UART4 Framing Error Interrupt Flag(3)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 1 – U4TXIF  UART4 Transmit Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred

Bit 0 – U4RXIF  UART4 Receive Interrupt Flag(4)

ValueDescription
1 Interrupt has occurred
0 Interrupt event has not occurred
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software needs to ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. U4IF is a read-only bit. To clear the interrupt condition, all bits in the U4UIR register must be cleared. U4EIF is a read-only bit. To clear the interrupt condition, all bits in the U4ERR register must be cleared. U4TXIF and U4RXIF are read-only bits and cannot be set/cleared by software.