8.10.2.4 System Configuration 0
The default value given in this fuse description is the factory-programmed value and may not be mistaken for the Reset value.
| Name: | SYSCFG0 |
| Offset: | 0x05 |
| Reset: | 0xD0 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCSRC[1:0] | CRCSEL | UPDIPINCFG | RSTPINCFG | BROWSAVE | EESAVE | ||||
| Access | R | R | R | R | R | R/W | R | ||
| Reset | 1 | 1 | 0 | 1 | 0 | 0 | 0 | ||
Bits 7:6 – CRCSRC[1:0] CRC Source
| Value | Name | Description |
|---|---|---|
| 0x0 | FLASH | CRC of full Flash (boot, application code and application data) |
| 0x1 | BOOT | CRC of the boot section |
| 0x2 | BOOTAPP | CRC of application code and boot sections |
| 0x3 | NOCRC | No CRC |
Bit 5 – CRCSEL CRC Polynomial Selection
| Value | Name | Description |
|---|---|---|
| 0x0 | CRC16 | CRC16 - CCITT |
| 0x1 | CRC32 | CRC32 (IEEE 802.3) |
Bit 4 – UPDIPINCFG Configuration of UPDI Pin at Start-Up
| Value | Name | Description |
|---|---|---|
| 0x0 | GPIO | The UPDI pin is configured as GPIO |
| 0x1 | UPDI | The UPDI pin is configured as UPDI with pull-up enabled on PF7 |
Bit 3 – RSTPINCFG Configuration of Reset Pin at Start-Up
| Value | Name | Description |
|---|---|---|
| 0x0 | INPUT | PF6 configured as input pin |
| 0x1 | RESET | External reset with pull-up on PF6 enabled |
Bit 1 – BROWSAVE Boot Row Save During Chip Erase
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The Boot Row is erased by a chip erase |
| 1 | ENABLE | The Boot Row is not erased by a chip erase |
Bit 0 – EESAVE EEPROM Saved During Chip Erase
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | EEPROM is erased during a chip erase |
| 0x1 | ENABLE | EEPROM is preserved during a chip erase regardless of whether the device is locked |