3.4.3 MIPI DSI/CSI Interface
The MIPI Display Serial Interface (DSI) host controller is a digital core that implements all protocol functions defined in the MIPI DSI Specification. The DSI host provides an interface between the LCD Controller (LCDC) and the MIPI D-PHY, allowing communication with a DSI-compliant display. The DSI sends data to a compliant display. A D-PHY configured as a host (TX) acts as the physical layer.
The Camera Serial Interface (CSI) implements the MIPI CSI-2 protocol specification. The CSI-2 link protocol specification is part of the communication protocols defined by MIPI Alliance standards intended for mobile system chip-to-chip communications. The CSI-2 specification is for the image application processor communication in cameras.
On the SAM9X75 Curiosity Pro, the MIPI DSI/CSI is connected to the 34-pin FPC connector J54.
Four headers (J55, J56, J57, J58) are arranged in a rectangular pattern on the PCB layout. These headers act as "pillars" for mounting a standard display onto the board.
| PIO | Signal Name | Signal Desctiption |
|---|---|---|
| – | MIPI_D3_P | MIPI D-PHY positive differential data 3 |
| – | MIPI_D3_N | MIPI D-PHY negative differential data 3 |
| – | MIPI_D2_P | MIPI D-PHY positive differential data 2 |
| – | MIPI_D2_N | MIPI D-PHY negative differential data 2 |
| – | MIPI_CK_P | MIPI D-PHY positive differential clock |
| – | MIPI_CK_N | MIPI D-PHY negative differential clock |
| – | MIPI_D1_P | MIPI D-PHY positive differential data 1 |
| – | MIPI_D1_N | MIPI D-PHY negative differential data 1 |
| – | MIPI_D0_P | MIPI D-PHY positive differential data 0 |
| – | MIPI_D0_N | MIPI D-PHY negative differential data 0 |
| – | MIPI_NRST_CON | MIPI reset from system reset |
| PC30 | MIPI_IO0_0.MIPI_ENABLE | DSI/CSI enable signal |
| PA20 | MIPI_IO0_0.MIPI_IRQ | DSI touchscreen interrupt line |
| PC18 | MIPI_IO0_0.MIPI_PWM | DSI PWM signal |
| PC1 | MIPI_IO0_0.MIPI_TWCK | DSI/CSI TWI clock signal |
| PC0 | MIPI_IO0_0.MIPI_TWD | DSI/CSI TWI data signal |