4.2.7 SAMA5D24/BGA256/LPDDR3-SDRAM Software Settings

The SAMA5D24/BGA256/LPDDR3-SDRAM set is part of a larger test board built on an 8-layer PCB. The board features a SAMA5D24/BGA256 MPU and one 8-Gbit(4) Micron LPDDR3-SDRAM device (Part No.: MT52L256M32D1PF-107WT). The DDR clock runs at 166 MHz.

Table 4-60. MPDDRC_MD Register Settings
FieldDescriptionSettingSetting Details
MDMemory Device5LPDDR3-SDRAM
DBW(1)Data Bus Width0Data bus width is 32 bits
Table 4-61. MPDDRC_CR Register Settings
FieldDescriptionSettingSetting Details
NCNumber of Column Bits110 bits to define the column number
NRNumber of Row Bits314 bits to define the row number
CASCAS Latency3LPDDR3 CAS Latency 3
DLLReset DLL(unchanged)Not available for LPDDR3-SDRAM
DIC_DSOutput Driver Impedance Control (Drive Strength)(unchanged)Not available for LPDDR3-SDRAM
DIS_DLLDisable DLL(unchanged)Used only during power-up sequence
ZQZQ Calibration(unchanged)Used only during power-up sequence
OCDOff-chip Driver(unchanged)Not available for LPDDR3-SDRAM
DQMSMask Data is Shared0DQM is not shared with another controller
ENRDMEnable Read Measure0DQS/DDR_DATA phase error correction is disabled
LC_LPDDR1Low-cost Low-power DDR1(unchanged)Not available for LPDDR3-SDRAM
NBNumber of Banks18 banks
NDQSNot DQS(unchanged)Not available for LPDDR3-SDRAM
DECODType of Decoding0Sequential
UNALSupport Unaligned Access1Unaligned access is supported
Table 4-62. MPDDRC_TPR0 Register Settings
FieldDescriptionSetting(2)Setting Details
TRASActive to Precharge Delay42 ns–
TRCDRow to Column Delaymax (18 ns, 3 ck)–
TWRWrite Recovery Delaymax (15 ns, 3 ck)–
TRCRow Cycle Delay60 ns–
TRPRow Precharge Delaymax (18 ns, 3 ck)–
TRRDActive BankA to Active BankBmax (10 ns, 2 ck)–
TWTRInternal Write to Read Delaymax (8 ns, 4 ck)–
TMRDLoad Mode Register Command to Activate or Refresh Commandmax (14 ns, 10 ck)–
Table 4-63. MPDDRC_TPR1 Register Settings
FieldDescriptionSetting(2)Setting Details
TRFCRow Cycle Delay210 ns–
TXSNR Exit Self-refresh Delay to Non-Read Command220 ns–
TXSRDExit Self-refresh Delay to Read Command(unchanged)Not available for LPDDR3-SDRAM
TXPExit Power-down Delay to First Commandmax (8 ns, 2 ck)–
Table 4-64. MPDDRC_TPR2 Register Settings
FieldDescriptionSetting(2)Setting Details
TXARDExit Active Power-down Delay to Read Command in Mode “Fast Exit”(unchanged)Not available for LPDDR3-SDRAM
TXARDSExit Active Power-down Delay to Read Command in Mode “Slow Exit”(unchanged)Not available for LPDDR3-SDRAM
TRPARow Precharge All Delay18 nsEquivalent to tRPAB
TRTPRead to Prechargemax (8 ns, 4 ck)–
TFAWFour Active Windowsmax (50 ns, 8 ck)–
Table 4-65. MPDDRC_LPDDR23_LPR Register Settings
FieldDescriptionSettingSetting Details
BK_MASK_PASRBank Mask Bit/PASR0Refresh is enabled
SEG_MASKSegment Mask Bit0Segment is refreshed
DSDrive Strength240 ohm typical
Table 4-66. MPDDRC_RD_DATA_PATH Register Settings
FieldDescriptionSettingSetting Details
SHIFT_SAMPLINGShift Sampling Point of Data2Sampling point is shifted by two cycles
Table 4-67. MPDDRC_IO_CALIBR Register Settings
FieldDescriptionSettingSetting Details
RDIVResistor Divider, Output Driver Impedance4LPDDR3 serial impedance line = 57 ohms
TZQIOIO Calibration101TZQIO = (DDRCK × 600e-9) + 1
EN_CALIBEnable Calibration(unchanged)Not available for LPDDR3-SDRAM
Table 4-68. MPDDRC_RTR Register Settings
FieldDescriptionSettingSetting Details
COUNT(3)MPDDRC Refresh Timer Count649Value needs to be computed
ADJ_REFAdjust Refresh Rate0Adjust refresh rate is not enabled
REF_PBRefresh Per Bank0Refresh all banks during autorefresh operation
Note:
  1. If using one 32-bit data bus width SDRAM device or two 16-bit devices, set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, set the Data Bus Width to 16 bits (DBW = 1).
  2. If timing values are given in nanoseconds, they must be converted in clock cycles and rounded up. tCYCLES = tns/tCK, where tCYCLES is the timing value in clock cycles, tns is the timing value in nanoseconds and tCK is the DDR clock period.

    Eg: If fCK = 166 MHz, then tCK = 1/fCK = 6 ns


    If tns = 35 ns, then tCYCLES = 35/6 = 6 clock cycles

  3. The value in the COUNT field needs to be computed.


    COUNT = tREFI/tCK

    For tREFI = 7.8 μs and tCK = 6 ns results in COUNT = 1300


    tREFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).

    tREFI [μs] = (Refresh Window [ms]/Refresh Cycles)*fCK [MHz]*1000


    If Refresh Window = 64 ms, Refresh Cycles = 8192 and fCK = 166 MHz,

    then COUNT = (64/8192)*166*1000 = 1297

  4. The memory controller is unable to use the whole capacity of the 8-Gbit memory device (supports 4 Gbits maximum). An 8-Gbit device was mounted for procurement facility reasons. With the current settings, the usage of half of this capacity is achievable.
Table 4-69. SAMA5D24/BGA256/LPDDR3-SDRAM Register Settings
Register NameRegister AddressContents Value
MPDDRC_MD0xF000C0200x00000005
MPDDRC_CR0xF000C0080x0090053D
MPDDRC_TPR00xF000C00C0xA423A337
MPDDRC_TPR10xF000C0100x02002523
MPDDRC_TPR20xF000C0140x00094400
MPDDRC_LPDDR23_LPR 0xF000C0280x02000000
MPDDRC_RD_DATA_PATH0xF000C05C0x00000002
MPDDRC_IO_CALIBR0xF000C0340x00876504
MPDDRC_RTR0xF000C0040x00000289
Important: For LPDDR2/LPDDR3 devices, certain sequences shall be used to power off these devices. Uncontrolled power-off sequences are destructive and can be applied only up to 400 times in the life of the device. Make sure to respect those sequences to ensure a long functional life for your system. Refer to the manufacturer’s data sheet for the proper way to power off the devices. Typically these rely upon an early detection of power failure and achieve a timely power-off sequence through the execution of a high priority interrupt.