4.2.6 SAMA5D24/BGA256/LPDDR2-SDRAM Software Settings

The SAMA5D24/BGA256/LPDDR2-SDRAM set is part of a larger test board built on an 8-layer PCB. The board features a SAMA5D24/BGA256 MPU and two 512-Mbit ISSI LPDDR2-SDRAM devices (Part No.: IS43LD16320A-25BLI). The DDR clock runs at 166 MHz.

Table 4-50. MPDDRC_MD Register Settings
Field	Description	Setting	Setting Details
MD	Memory Device	7	LPDDR2-SDRAM
DBW⁽¹⁾	Data Bus Width	0	Data bus width is 32 bits

Table 4-51. MPDDRC_CR Register Settings
Field	Description	Setting	Setting Details
NC	Number of Column Bits	1	10 bits to define the column number
NR	Number of Row Bits	2	13 bits to define the row number
CAS	CAS Latency	3	LPDDR2 CAS Latency 3
DLL	Reset DLL	(unchanged)	Not available for LPDDR2-SDRAM
DIC_DS	Output Driver Impedance Control (Drive Strength)	(unchanged)	Not available for LPDDR2-SDRAM
DIS_DLL	Disable DLL	(unchanged)	Not available for LPDDR2-SDRAM
ZQ	ZQ Calibration	(unchanged)	Used only during power-up sequence
OCD	Off-chip Driver	(unchanged)	Not available for LPDDR2-SDRAM
DQMS	Mask Data is Shared	0	DQM is not shared with another controller
ENRDM	Enable Read Measure	0	DQS/DDR_DATA phase error correction is disabled
LC_LPDDR1	Low-cost Low-power DDR1	(unchanged)	Not available for LPDDR2-SDRAM
NB	Number of Banks	0	4 banks
NDQS	Not DQS	(unchanged)	Not available for LPDDR2-SDRAM
DECOD	Type of Decoding	0	Sequential
UNAL	Support Unaligned Access	1	Unaligned access is supported

Table 4-52. MPDDRC_TPR0 Register Settings
Field	Description	Setting⁽²⁾	Setting Details
TRAS	Active to Precharge Delay	42 ns	–
TRCD	Row to Column Delay	18 ns	–
TWR	Write Recovery Delay	15 ns	–
TRC	Row Cycle Delay	60 ns	–
TRP	Row Precharge Delay	18 ns	–
TRRD	Active BankA to Active BankB	10 ns	–
TWTR	Internal Write to Read Delay	8 ns	–
TMRD	Load Mode Register Command to Activate or Refresh Command	2 ck	–

Table 4-53. MPDDRC_TPR1 Register Settings
Field	Description	Setting⁽²⁾	Setting Details
TRFC	Row Cycle Delay	90 ns	–
TXSNR	Exit Self-refresh Delay to Non-Read Command	100 ns	–
TXSRD	Exit Self-refresh Delay to Read Command	(unchanged)	Not available for LPDDR2-SDRAM
TXP	Exit Power-down Delay to First Command	8 ns	–

Table 4-54. MPDDRC_TPR2 Register Settings
Field	Description	Setting⁽²⁾	Setting Details
TXARD	Exit Active Power-down Delay to Read Command in Mode “Fast Exit”	(unchanged)	Not available for LPDDR2-SDRAM
TXARDS	Exit Active Power-down Delay to Read Command in Mode “Slow Exit”	(unchanged)	Not available for LPDDR2-SDRAM
TRPA	Row Precharge All Delay	18 ns	Equivalent to tRPAB
TRTP	Read to Precharge	8 ns	–
TFAW	Four Active Windows	50 ns	–

Table 4-55. MPDDRC_LPDDR23_LPR Register Settings
Field	Description	Setting	Setting Details
BK_MASK_PASR	Bank Mask Bit/PASR	0	Refresh is enabled
SEG_MASK	Segment Mask Bit	0	Segment is refreshed
DS	Drive Strength	2	40 ohms typical

Table 4-56. MPDDRC_RD_DATA_PATH Register Settings
Field	Description	Setting	Setting Details
SHIFT_SAMPLING	Shift Sampling Point of Data	1	Sampling point is shifted by one cycle

Table 4-57. MPDDRC_IO_CALIBR Register Settings
Field	Description	Setting	Setting Details
RDIV	Resistor Divider, Output Driver Impedance	4	LPDDR2 serial impedance line = 60 ohms
TZQIO	IO Calibration	101	TZQIO = (DDRCK × 600e-9) + 1
EN_CALIB	Enable Calibration	(unchanged)	Not available for LPDDR2-SDRAM

Table 4-58. MPDDRC_RTR Register Settings
Field	Description	Setting	Setting Details
COUNT⁽³⁾	MPDDRC Refresh Timer Count	649	Value needs to be computed
ADJ_REF	Adjust Refresh Rate	0	Adjust refresh rate is not enabled
REF_PB	Refresh Per Bank	0	Refresh all banks during autorefresh operation

Note:

If using one 32-bit data bus width SDRAM device or two 16-bit devices, set the Data Bus Width to 32 bits (DBW = 0). If only one 16-bit data bus width SDRAM device is used, set the Data Bus Width to 16 bits (DBW = 1).
If timing values are given in nanoseconds, they must be converted in clock cycles and rounded up. t_CYCLES = t_ns/t_CK, where t_CYCLES is the timing value in clock cycles, t_ns is the timing value in nanoseconds and t_CK is the DDR clock period.
Eg: If f_CK = 166 MHz, then t_CK = 1/f_CK = 6 ns 
If t_ns = 35 ns, then t_CYCLES = 35/6 = 6 clock cycles
The value in the COUNT field needs to be computed. 
COUNT = t_REFI/t_CK
For t_REFI = 7.8 μs and t_CK = 6 ns results in COUNT = 1300 
t_REFI can also be calculated if the Refresh Window [ms] and Refresh Cycles are given (in the SDRAM data sheet).
t_REFI [μs] = (Refresh Window [ms]/Refresh Cycles)*f_CK [MHz]*1000 
If Refresh Window = 64 ms, Refresh Cycles = 8192 and f_CK = 166 MHz,
then COUNT = (64/8192)*166*1000 = 1297

Table 4-59. SAMA5D24/BGA256/LPDDR2-SDRAM Register Settings
Register Name	Register Address	Contents Value
MPDDRC_MD	0xF000C020	0x00000007
MPDDRC_CR	0xF000C008	0x00800539
MPDDRC_TPR0	0xF000C00C	0x2223A337
MPDDRC_TPR1	0xF000C010	0x0800110F
MPDDRC_TPR2	0xF000C014	0x00092300
MPDDRC_LPDDR23_LPR	0xF000C028	0x02000000
MPDDRC_RD_DATA_PATH	0xF000C05C	0x00000001
MPDDRC_IO_CALIBR	0xF000C034	0x00876504
MPDDRC_RTR	0xF000C004	0x00000289

Important: For LPDDR2/LPDDR3 devices, certain sequences shall be used to power off these devices. Uncontrolled power-off sequences are destructive and can be applied only up to 400 times in the life of the device. Make sure to respect those sequences to ensure a long functional life for your system. Refer to the manufacturer’s data sheet for the proper way to power off the devices. Typically these rely upon an early detection of power failure and achieve a timely power-off sequence through the execution of a high priority interrupt.

AN2717

4.2.6 SAMA5D24/BGA256/LPDDR2-SDRAM Software Settings